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PDF ( 数据手册 , 数据表 ) MT36HTJ51272

零件编号 MT36HTJ51272
描述 4GB DDR2 SDRAM Registered DIMM
制造商 Micron
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MT36HTJ51272 数据手册, 描述, 功能
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT36HTJ51272(P) – 4GB
For the latest data sheet and for component data sheets, refer to Micron's Web site: www.micron.com
Features
• Supports 95°C with double refresh
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, or
PC2-5300
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Dual rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1: 240-Pin DIMM (MO-237 R/C “K”)
Height: 30mm (1.18in)
Options
Marking
• Parity
• Package
240-pin DIMM (lead-free)
• Frequency/CAS latency1
3.0ns @ CL = 5 (DDR2-667)2
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
30mm (1.18in)
P
Y
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
2. Contact Micron for product availability.
Table 1: Key Timing Parameters
Speed
Grade
-667
-53E
-40E
Table 2:
Industry Nomenclature
PC2-5300
PC2-4200
PC2-3200
Addressing
Data Rate (MT/s)
CL = 5
667
CL = 4
533
533
400
CL = 3
400
400
400
tRCD
(ns)
15
15
15
tRP
(ns)
15
15
15
tRC
(ns)
55
55
55
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
4GB
8K
16K (A0–A13)
8 (BA0–BA2)
1KB
1Gb (256 Meg x 4)
2K (A0–A9, A11)
2 (S0#, S1#)
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT36HTJ51272 pdf, 数据表
4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
AC Timing and Operating Conditions
AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron’s Web site: www.micron.com. Module
speed grades correlate with component speed grades as shown in Table 8:
Table 8: Module and Component Speed Grade Table
Module Speed Grade
-667
-53E
-40E
Component Speed Grade
-3
-37E
-5E
Register and PLL Specifications
Table 9: Register (SSTU32868 devices or equivalent JESD82-16)
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Symbol
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
VOH
VOL
II
IDD
IDD
Dynamic operating –
clock tree
Dynamic operating
(per each input)
IDDD
IDDD
Input capacitance
(per device, per pin)
CI
Pins
Condition
Address, control,
command
SSTL_18
Address, control,
command
SSTL_18
Address, control,
command
SSTL_18
Address, control,
command
SSTL_18
Parity output
LVCMOS
Parity output
LVCMOS
All pins
VI = VDDQ or VSSQ
All pins
RESET# = VSSQ (I/O = 0)
All pins
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
I/O = 0
n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), I0 = 0; CK and CK#
switching 50% duty cycle
n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), I0 = 0; CK and CK#
switching 50% duty cycle;
One data input switching at
tCK/2, 50% duty cycle
All inputs except
RESET#
VI = VREF ±250mV;
VDDQ = 1.8V
RESET#
VI = VDDQ or VSSQ
Min
VREF(DC) +125
0
VREF(DC) + 250
0
1.2
–5
2.5
Max
VDDQ + 250
VREF(DC) - 125
VDD
VREF(DC) - 250
0.5
5
100
40mA
Varies by
manufacturer
Varies by
manufacturer
3.5
Varies by
manufacturer
Units
mV
mV
mV
mV
mV
mV
µA
µA
µA
µA
µA
pF
pF
Notes:
1. Specifications for the register listed above are critical for proper operation of DDR2 SDRAM
registered DIMMs. These are meant to be a subset of the parameters for the specific device
used on the module. Detailed information for this register is available in JEDEC Standard
JESD82.
PDF: 09005aef822553c2/Source: 09005aef822553af
HT36HTJ51272.fm - Rev. B 7/06 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.














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