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PDF ( 数据手册 , 数据表 ) MT18VDVF6472D

零件编号 MT18VDVF6472D
描述 512MB DDR SDRAM VLP Registered DIMM
制造商 Micron
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MT18VDVF6472D 数据手册, 描述, 功能
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Features
DDR SDRAM VLP Registered DIMM
MT18VDVF6472D – 512MB
MT18VDVF12872D – 1GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 184-pin, very low profile dual in-line memory
module (VLP DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial presence detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
• Dual rank
Figure 1: 184-Pin VLP DIMM (MO-206)
Very Low Profile Height 0.72in (18.29mm)
Options
Marking
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory clock, speed, CAS latency2
6ns (166MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB height
Very Low-Profile 0.72in (18.29mm)1
G
Y
-335
-2621
-26A1
-265
Notes:1. Contact Micron for product availability.
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_1.fm - Rev. A 8/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT18VDVF6472D pdf, 数据表
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
Pin Numbers
2, 4, 6, 8, 12,13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
92
181, 182, 183
91
1
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
7, 38, 46, 70, 85, 108, 120,
148, 168
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93, 100,
116, 124, 132, 139, 145,
152, 160, 176
184
16, 17, 75, 76, 90
9, 71, 82, 101, 102, 103,
113, 115 (256MB), 163,
167, 173
Symbol
DQ0–DQ63
SCL
SA0–SA2
SDA
VREF
VDDQ
VDD
VSS
VDDSPD
DNU
NC
Type
Input/ Data I/Os: Data bus.
Output
Description
Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply SSTL_2 reference voltage.
Supply DQ Power Supply: +2.5V ±0.2V.
Supply Power Supply: +2.5V ±0.2V.
Supply Ground.
Supply
Serial EEPROM positive power supply: +2.3V to +3.6V.
Do Not Use: Thes pins are not connected on these modules, but
are assigned pins on other modules in this product family.
No Connect: These pins should be left unconnected.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.







MT18VDVF6472D equivalent, schematic
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Commands
Commands
Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen-
eral reference of available commands. For a more detailed description of commands and
operations, refer to the 256Mb or 512Mb DDR SDRAM component data sheets.
Table 7:
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or
reserved
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
CS# RAS# CAS# WE# ADDR
HX
LH
LL
LH
LH
LH
LL
LL
XX
X
HH
X
H H Bank/Row
L H Bank/Col
L L Bank/Col
HL
X
H L Code
LH
X
LL
L L Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
Notes: 1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (512MB) or A0–A9, A11 (1GB) provide col-
umn address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10
LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device
banks are precharged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–A12 provide the op-code to be written to the selected
mode register.
Table 8:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
DM DQs
L Valid
HX
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.










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