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PDF ( 数据手册 , 数据表 ) MT18HVF12872

零件编号 MT18HVF12872
描述 1GB DDR2 VLP Registered DIMM
制造商 Micron
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MT18HVF12872 数据手册, 描述, 功能
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
Features
DDR2 VLP Registered DIMM (RDIMM)
MT18HVF12872(P) – 1GB
For the latest data sheet and for component data sheets, refer to Micron's Web site: www.micron.com/products/ddr2
Features
• Supports 95°C with double refresh
• Fits with the ATCA form factor
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Table 1: Addressing
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Figure 1:
240-Pin VLP DIMM (MO-237)
Functionally equivelent to R/C “U” and “V”
Height: 17.9mm (0.705in)
Options
Marking
• Parity
• Package
240-pin DIMM (lead-free)
• Frequency/CAS latency1
3.0ns @ CL = 5 (DDR2-667)2
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
17.9mm (1.18in)
P
Y
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
2. Contact Micron for product availability.
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1KB
512Mb (128 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
Table 2: Key Timing Parameters
Speed Grade
-667
-53E
-40E
Industry Nomenclature
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 5
667
CL = 4
533
533
400
CL = 3
400
400
tRCD
(ns)
15
15
15
tRP
(ns)
15
15
15
tRC
(ns)
55
55
55
PDF: 09005aef82255aba/Source: 09005aef82255a83
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT18HVF12872 pdf, 数据表
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 6: Absolute Maximum DC Ratings
Parameter
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
VDDL supply voltage relative to Vss
Voltage on any pin relative to VSS
Storage temperature (2X refresh at 95°C)
DDR2 SDRAM device operating temperature
Input leakage current; Any input 0V VIN VDD;
VREF input 0V VIN 0.95V; all other pins not
under test = 0V
Output leakage current; 0V VOUT VDDQ; DQs
and ODT are disabled
VREF leakage current; VREF = valid VREF level
Command/address,
RAS#, CAS#, WE# S#,
CKE, CK, CK#, DM
DQ, DQS, DQS#
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
TCASE
II
Ioz
IVREF
Min
–1.0
–0.5
–0.5
–0.5
–55
0
–10
–10
–46
Max
2.3
2.3
2.3
2.3
100
95
10
Units
V
V
V
V
°C
°C
µA
10 µA
46 µA
Capacitance
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a
considerably more accurate result. JEDEC modules are now designed by using simula-
tions to close timing budgets.
Table 7:
DRAM Interface for DRAM I/O
DRAM (at each individual device pin)
Parameter
Input high (logic 1) voltage
Input low (logic 0) voltage
Input high (logic 1) voltage (-667 speed grade)
Input low(logic 0) voltage (-667 speed grade)
Input leakage current; any input 0V VIN VDD; all other pins
not under test = 0V
Output leakage current; 0V VOUT VDDQ; DQ and ODT
disabled
Input/output capacitance
Symbol
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
Ii
Ioz
CIO
Min
VREF(DC) + 125
–300
VREF(DC) + 200
–10
–10
5.5
Max
VDDQ + 300
VREF(DC) - 125
VREF(DC) - 200
10
10
10.5
Units
mV
mV
mV
mV
uA
uA
pF
PDF: 09005aef82255aba/Source: 09005aef82255a83
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.














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