DataSheet8.cn


PDF ( 数据手册 , 数据表 ) MT18HTF12872

零件编号 MT18HTF12872
描述 1GB DDR2 SDRAM Registered DIMM
制造商 Micron
LOGO Micron LOGO 


1 Page

No Preview Available !

MT18HTF12872 数据手册, 描述, 功能
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT18HTF6472 – 512MB
MT18HTF12872(P) – 1GB
MT18HTF25672(P) – 2GB
For component data sheets, refer to Micron's Web site: www.micron.com
Features
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin RDIMM (MO-237
R/C C–Non-Parity, R/C H–Parity)
PCB height: 30mm (1.18in)
Options
• Parity3
• Operating temperature1
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
240-pin DIMM (Pb-free)
• Frequency/CAS latency2
2.5ns @CL = 5 (DDR2-800)3
2.5ns @ CL = 6 (DDR2-800)3
3.0ns @ CL = 5 (DDR2-667)3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
30mm (1.18in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not available in 512MB density.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
Data Rate (MT/s)
CL = 5
800
667
667
CL = 4
533
533
533
533
400
CL = 3
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
tRC
(ns)
12.5 55
15 55
15 55
15 55
15 55
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT18HTF12872 pdf, 数据表
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
IDD Specifications
IDD Specifications
Table 10:
DDR2 IDD Specifications and Conditions – 512MB
Values shown for MT47H64M4 DDR2 SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
Parameter/Condition
Operating one bank active-precharge current: tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address bus
Fast PDN exit
MR[12] = 0
inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
-53E
1,440
1,620
90
630
630
450
108
720
2,880
2,700
3,060
90
4,320
-40E
1,350
1,530
90
450
540
360
108
540
2,250
2,070
2,970
90
4,140
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.







MT18HTF12872 equivalent, schematic
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Table 19: Serial Presence-Detect Matrix (continued)
Byte
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Description
MIN row precharge time, tRP
MIN row active-to-row active, tRRD
MIN RAS#-to-CAS# delay, tRCD
MIN active-to-precharge, tRAS
Module rank density
Address and command setup time, tISb
Address and command hold time, tIHb
Data/data mask input setup time, tDSb
Data/data mask input hold time, tDHb
Write recovery time, tWR
WRITE-to-READ command delay, tWTR
READ-to-PRECHARGE command delay,
tRTP
Memory analysis probe
Extension for bytes 41 and 42
MIN active-to-active/refresh time, tRC2
MIN AUTO REFRESH-to-ACTIVE/
AUTO REFRESH command period, tRFC
SDRAM device MAX cycle time, tCK
(MAX)
SDRAM device MAX DQS–DQ skew time,
tDQSQ
SDRAM device MAX read data hold
skew factor, tQHS
PLL relock time
Entry (Version)
-80E
-800/-667
-53E/-40E
-80E
-800/-667
-53E/-40E
-80E/-800
-667/-53E
-40E
512MB, 1GB, 2GB
-80E/-800
-667
-53E
-40E
-80E/-800
-667
-53E
-40E
-80E/-800
-667/-53E
-40E
-80E/-800
-667
-53E
-40E
-80E/-667/-53E
-800/-40E
-80E
-800/-667
-53E/-40E
-80E
-800/-667/-53E
-40E
-80E/-800
-667
-53E
-40E
-80E/-800
-667
-53E
-40E
512MB1
3C
1E
3C
–/2D
28
80
25
35
37
47
–/10
15
22
27
3C
–/–/1E
28
1E
00
00
00
–/–/3C
37
4B
80
1E
23
28
2D
0F
1GB
32
3C
3C
1E
32
3C
3C
2D
2D
28
01
17
20
25
35
25
27
37
47
05
10
15
12
17
22
27
3C
1E
28
1E
00
30
00
00
39
3C
37
69
80
14
18
1E
23
1E
22
28
2D
0F
2GB
32
3C
3C
1E
32
3C
3C
2D
2D
28
02
17
20
25
35
25
27
37
47
05
10
15
12
17
22
27
3C
1E
28
1E
00
36
06
06
39
3C
37
7F
80
14
18
1E
23
1E
22
28
2D
0F
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.










页数 18 页
下载[ MT18HTF12872.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
MT18HTF128721GB DDR2 SDRAM Registered DIMMMicron
Micron
MT18HTF12872P1GB DDR2 SDRAM Registered DIMMMicron
Micron

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap