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PDF ( 数据手册 , 数据表 ) MT16VDDT3264A

零件编号 MT16VDDT3264A
描述 256MB DDR SDRAM UNBUFFERED DIMM
制造商 Micron
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MT16VDDT3264A 数据手册, 描述, 功能
256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT16VDDT3264A – 256MB
MT16VDDT6464A – 512MB
MT16VDDT12864A
MT16VDDT25664A
1GB
2GB
(ADVANCE)
For the latest data sheet, please refer to the MicronWeb
site: www.micron.com/products/modules
Features
• 184-pin, dual in-line memory module (DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 256MB (32 Meg x 64), 512MB (64 Meg x 64), 1GB
(128 Meg x 64), and 2GB (256 Meg x 64)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (256MB), 7.8125µs (512MB, 1GB, and 2GB)
maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
Standard 1.25in. (31.75mm)
Low-Profile 1.15in. (29.21mm)
OPTIONS
MARKING
• Package
184-pin DIMM (standard)
G
184-pin DIMM (lead-free)1
• Memory Clock, Speed, CAS Latency2
Y
6ns/166MHz (333 MT/s) CL = 2.5
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2
-335
-2621
-26A1
7.5ns/133 MHz (266 MT/s) CL = 2.5
-265
• PCB
Standard 1.25in. (31.75mm)
See page 2 note
Low-Profile 1.20in. (30.48mm)
See page 2 note
NOTE: 1. Consult Micron for product availability.
2. CL = CAS (READ) Latency.
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
2GB
8K
16K (A0–A13)
4 (BA0, BA1)
1Gb (128 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.







MT16VDDT3264A pdf, 数据表
256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
General Description
The MT16VDDT3264A, MT16VDDT6464A,
MT16VDDT12864A, and MT16VDDT25664A are high-
speed CMOS, dynamic random-access, 256MB,
512MB, 1GB and 2GB memory modules organized in
x64 configuration. DDR SDRAM modules use inter-
nally configured quad-bank DDR SDRAM devices.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0–A11 select
device row for 256MB; A0–A12 select device row for
512MB, 1GB; A0–A13 select device row for 2GB). The
address bits registered coincident with the READ or
WRITE command are used to select the device bank
and the starting device column location for the burst
access.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM com-
ponent data sheets.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 5, Mode Register Definition Diagram, on page 9.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.







MT16VDDT3264A equivalent, schematic
256MB, 512MB, 1GB, 2GB (x64, DR)
184-PIN DDR SDRAM UDIMM
Table 14: IDD Specifications and Conditions – 1GB
DDR SDRAM Components only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C TA +70°C; VDD = VDDQ = +2.5V ±0.2VV
MAX
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge; tRC =
tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once
per clock cyle; Address and control inputs changing once every two
clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =
tCK MIN; CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM
andDQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
AUTO REFRESH CURRENT
tREFC = tRFC (MIN)
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active READ, or WRITE
commands
SYM
IDD0a
IDD1a
IDD2Pb
IDD2Fb
IDD3Pb
IDD3Nb
IDD4Ra
IDD4Wa
IDD5b
IDD5Ab
IDD6b
IDD7a
-335
1,080
1,320
80
720
560
800
1,360
1,440
4,640
160
80
3,280
-262
1,080
1,320
80
720
560
800
1,360
1,280
4,640
160
80
3,240
-26A/
-265
960
UNITS NOTES
mA 20, 42
1,200 mA 20, 42
80 mA 21, 28,
44
640 mA 45
480 mA 21, 28,
44
720 mA 40
1,200 mA 20, 42
1,120 mA
20
4,480
160
80
2,840
mA 20, 44
mA 20, 44
mA 9
mA 20, 43
NOTE:
a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80739fa5, source: 09005aef807397e5
DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.










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