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PDF ( 数据手册 , 数据表 ) MT16HTF12864A

零件编号 MT16HTF12864A
描述 1GB DDR2 SDRAM Unbuffered DIMM
制造商 Micron
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MT16HTF12864A 数据手册, 描述, 功能
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM Unbuffered DIMM
MT16HTF6464A – 512MB
MT16HTF12864A – 1GB
MT16HTF25664A – 2GB
For component specifications, refer to the Micron’s Web site: www.micron.com/ddr2
Features
• 240-pin, unbuffered, dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• 512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB
(256 Meg x 64)
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
Figure 1: 240-Pin DIMM (MO-237 R/C “B”)
PCB height: 29.97mm (1.18in)
Options
• Package
240-pin DIMM (lead-free)
• Frequency/CL1
2.5ns @ CL = 5 (DDR2-800)2
3.0ns @ CL = 5 (DDR2-667)3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
29.97mm (1.18in)
Marking
Y
-80E
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency.
2. Not available in 512MB density.
3. Not available in 2GB density.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT16HTF12864A pdf, 数据表
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 6: Absolute Maximum Ratings
Parameter
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
VDDL supply voltage relative to Vss
Voltage on any pin relative to VSS
Storage temperature
DDR2 SDRAM device operating temperature (ambient)
Operating temperature (ambient)
Input leakage current; Any input 0V VIN VDD;
VREF input 0V VIN 0.95V;
(All other pins not under test = 0V)
Command/address,
RAS#, CAS#, WE#
S#, CKE1
CK0, CK0#
CK1, CK1#, CK2, CK2#
DM
Output leakage current; 0V VOUT VDDQ; DQ and DQ, DQS, DQS#
ODT are disabled
VREF leakage current; VREF = Valid VREF level
Symbol
VDD
VDDQ
VDDL2
VIN, VOUT
TSTG
Tcase
TOPR
II
IOZ
Min
–1.0
–0.5
–0.5
–0.5
–55
0
0
–80
–40
–20
–30
–10
–10
–32
Max
2.3
2.3
2.3
2.3
100
85
55
80
40
20
30
10
10
32
Units
V
V
V
V
°C
°C
°C
µA
µA
µA
Notes:
1. S# is defined to be S0# and S1#. CKE includes both CKE0 and CKE1.
2. VDDL is the power supply for the DDR2 devices’ DLL; however, this power supply is not
brought directy to a DIMM pin.
Capacitance
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a
considerably more accurate result. JEDEC modules are now designed by using simula-
tions to close timing budgets.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.







MT16HTF12864A equivalent, schematic
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Table 13: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current:
Power supply current, READ: SCL clock frequency = 100 KHz
Power supply current, WRITE: SCL clock frequency = 100 KHz
Symbol
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICCR
ICCW
Min
1.7
VDDSPD × 0.7
–0.6
0.10
0.05
1.6
0.4
2
Max
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
3
3
4
1
3
Units
V
V
V
V
µA
µA
µA
mA
mA
Table 14: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
Min
0.2
1.3
200
0
0.6
0.6
1.3
100
0.6
0.6
Max
0.9
300
50
0.3
400
10
Units
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
Notes
1
2
2
3
4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,
the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and
the EEPROM does not respond to its slave address.
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.










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