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PDF ( 数据手册 , 数据表 ) LS013B4DN04

零件编号 LS013B4DN04
描述 LCD Module
制造商 Sharp
LOGO Sharp LOGO 


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LS013B4DN04 数据手册, 描述, 功能
No.
Date
LCP-1109027
Jan 13th 2010
Technical Literature
For
TFT-LCD Module
Model No. LS013B4DN04
Notice
The technical Literature is subject to change without any prior
notice for the purpose of product improvement.
Please contact Sharp or its representative before designing
your product based on this literature.
Mobile Liquid Crystal Display Group
SHARP CORPORATION







LS013B4DN04 pdf, 数据表
SPEC No.
LCP-1109027
MODEL No.
LS013B4DN04
PAGE
7
1. Outline
This TFT-LCD module is a reflective active matrix memory liquid crystal display module with CG silicone thin film
transistor. Module outline is indicated in fig 8-1.
2. Characteristics
Reflective panel of white and black with aspect ratio of 1:1
1.3” screen has 96x 96 resolusion. (9216 pixels stripe array)
Display control by serial data signal communication.
Arbitrary line data renewable.
1bit internal memory for data storage within the panel.
Thin, light-weight and compact module with monolithic technology.
Super low power consumption TFT panel.
FPC attached (Applicable connectors: Please refer to the page 21 “Recommended Connectors”
3. Mechanical Specification
Table 3-1
Item
Screen size
Viewing Area
Dot configuration
Dot pitch
Pixel Array
Outline Dimension
Specification
3.4 (1.3”)
24.192 (H) × 24.192 (V)
96 (H) × 96 (V)
0.252 (H) × 0.252 (V)
Stripe Array
28.2 (W) × 32.34 (H) × 1.40 (D)
Mass
3.6 (TYP
Surface Hardness
3H
(Note) Detail dimension and tolerance are shown in fig. 8-1
unit
cm
mm
Dot
mm
-
mm
g
Pencil hardness







LS013B4DN04 equivalent, schematic
SPEC No.
LCP-1109027
MODEL No.
LS013B4DN04
PAGE
15
6-5) Input Signal Timing Chart
6-5-1 Data update mode (1 line)
Updates data of only one specified line. (M0=”H” M2 ”L”)
SCS
SI
SCLK
twSCSH
tsSCS
M0 M1 M2 DMYDMYDMYDMYDMYAG0 AG1 AG2 AG3 AG4 AG5 AG6 DMY D1 D2 D3 D4
tsSI thSI
twSCLKL
twSCLKH
D93 D94 D95 D96
Mode selection period
(3ck+5ckDMY)
Gate line address period
(7ck+1ckDMY)
Data writing period
(96ck)
DUMMY DATA(don't care)
Data transfer period
(16ck)
thSCS
twSCSL
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag.
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
Data write period
Data is being stored in 1st latch block of binary driver on panel.
Data transfer period
Data written in 1st latch is being transferred (written) to pixel internal memory circuit.
For gate line address setting, refer to 6-6) Input Signal and Display.
M1: Frame inversion fl is enaled when EXTMODE=”L”.
When SCS becomes L , M0 and M2 are cleared.










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