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PDF ( 数据手册 , 数据表 ) i.MX35

零件编号 i.MX35
描述 Applications Processors
制造商 Freescale Semiconductor
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i.MX35 数据手册, 描述, 功能
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCIMX35SR2AEC
Rev. 10, 06/2012
IMX35
i.MX35 Applications
Processors for
Automotive Products
Package Information
Plastic Package
Case 5284 17 x 17 mm, 0.8 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1 Introduction
The i.MX35 Auto Application Processor family is
designed for automotive infotainment and navigation
applications. These processors are AECQ100 Grade 3
qualified and rated for ambient operating temperatures
up to 85 °C.
Based on an ARM11 microprocessor core running at up
to 532 MHz, the device offers the following features and
optimized system cost for the target applications.
• Audio connectivity and telematics:
— Compressed audio playback from storage
devices (CD, USB, HDD or SD card)
— PlayFromDevice (1-wire and 2-wire
support) for portable media players
— iPod/iPhone control and playback
— High-speed CD ripping to USB, SD/MMC
or HDD for virtual CD changer
— Audio processing for hands-free telephony:
Bluetooth, AEC/NS, and microphone beam
forming
— Speech recognition
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional Description and Application Information. . . . . . 4
2.1. Application Processor Domain Overview . . . . . . . . . 5
2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6
2.3. Advanced Power Management Overview . . . . . . . . 6
2.4. ARM11 Microprocessor Core. . . . . . . . . . . . . . . . . . 6
2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Signal Descriptions: Special Function Related Pins . . . . 12
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 13
4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 19
4.6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 20
4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . . 21
4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . . 24
4.9. Module-Level AC Electrical Specifications . . . . . . . 30
5. Package Information and Pinout . . . . . . . . . . . . . . . . . . 131
5.1. MAPBGA Production Package 1568-01, 17 × 17 mm,
0.8 Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.2. MAPBGA Signal Assignments . . . . . . . . . . . . . . . 133
6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 145
7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
© Freescale Semiconductor, Inc., 2010. All rights reserved.







i.MX35 pdf, 数据表
Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain1
Subsystem
Brief Description
ATA ATA module SDMA
AUDMUX Digital audio ARM
mux
CAN(2) CAN module ARM
CCM
Clock control ARM
module
CSPI(2)
Configurable
serial
peripheral
interface
SDMA,
ARM
ECT
Embedded SDMA,
cross trigger ARM
EMI External
memory
interface
SDMA
EPIT(2)
Enhanced
ARM
periodic
interrupt timer
Connectivity
peripherals
Multimedia
peripherals
Connectivity
peripherals
Clocks
Connectivity
peripherals
Debug
External
memory
interface
Timer
peripherals
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.
The CAN protocol is primarily designed to be used as a vehicle
serial data bus running at 1 Mbps.
This block generates all clocks for the peripherals in the SDMA
platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.
This module is a serial interface equipped with data FIFOs; each
master/slave-configurable SPI module is capable of interfacing to
both serial port interface master and slave devices. The CSPI ready
(SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts.
ECT (embedded cross trigger) is an IP for real-time debug
purposes. It is a programmable matrix allowing several subsystems
to interact with each other. ECT receives signals required for
debugging purposes (from cores, peripherals, buses, external
inputs, and so on) and propagates them (propagation programmed
through software) to the different debug resources available within
the SoC.
The EMI module provides access to external memory for the ARM
and other masters. It is composed of the following main
submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.
Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.
i.MX35 Applications Processors for Automotive Products, Rev. 10
8 Freescale Semiconductor







i.MX35 equivalent, schematic
Table 10. i.MX35 Power Modes (continued)
Power
Mode
Description
Stop
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
Static
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
Note: Typical column: TA = 25 °C
Note: Maximum column: TA = 85 °C
QVCC (ARM/L2
Peripheral)
Typ.
Max.
MVDD/PVDD
Typ.
Max.
1.1 mA 77 mA 400 µA 2.2 mA
820 µA 72 mA 50 µA 1.7 mA
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
1.2 mA 2.2 mA
24 µA
35 µA
4.3 Supply Power-Up/Power-Down Requirements and Restrictions
This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
CAUTION
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
i.MX35 Applications Processors for Automotive Products, Rev. 10
16 Freescale Semiconductor










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