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PDF ( 数据手册 , 数据表 ) XS1-L01A-LQ64

零件编号 XS1-L01A-LQ64
描述 MCU 32BIT 8KB OTP
制造商 Xmos
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XS1-L01A-LQ64 数据手册, 描述, 功能
XS1-L01A-LQ64 Datasheet
2012/10/15
XMOS © 2012, All Rights Reserved
Document Number: X1135,







XS1-L01A-LQ64 pdf, 数据表
XS1-L01A-LQ64 Datasheet
7
X1135,
5.2 Channel Ends, Links and Switch
Logical cores communicate using point-to-point connections formed between two
channel ends. Between tiles, channel communications are implemented over
xConnect Links and routed through switches. The links operate in either 2bit/di-
rection or 5bit/direction mode, depending on the amount of bandwidth required.
Circuit switched, streaming and packet switched data can both be supported effi-
ciently. Streams provide the fastest possible data rates between xCORE Tiles (up to
250 MBit/s), but each stream requires a single link to be reserved between switches
on two tiles. All packet communications can be multiplexed onto a single link. A
total of four 5bit links are available between both cores.
Information on the supported routing topologies that can be used to connect
multiple devices together can be found in the XS1-L Link Performance and Design
Guide, X2999.
5.3 Ports and Clock Blocks
Ports provide an interface between the logical cores and I/O pins. All pins of a port
provide either output or input. Signals in different directions cannot be mapped
onto the same port.
The operation of each port is synchronized to a clock block. A clock block can be
connected to an external clock input, or it can be run from the divided reference
clock. A clock block can also output its signal to a pin. On reset, each port is
connected to clock block 0, which runs from the xCORE Tile reference clock.
The ports and links are multiplexed, allowing the pins to be configured for use by
ports of different widths or links. If an xConnect Link is enabled, the pins of the
underlying ports are disabled. If a port is enabled, it overrules ports with higher
widths that share the same pins. The pins on the wider port that are not shared
remain available for use when the narrower port is enabled. Ports always operate
at their specified width, even if they share pins with another port.
5.4 Timers
Timers are 32-bit counters that are relative to the xCORE Tile reference clock. A
timer is defined to tick every 10 ns. This value is derived from the reference clock,
which is configured to tick at 100 MHz by default.
5.5 PLL
The PLL creates a high-speed clock that is used for the switch, tile, and reference
clock. The PLL multiplication value is selected through the two MODE pins, and
can be changed by software to speed up the tile or use less power. The MODE pins
are set as shown in Figure 2:
Figure 2 also lists the values of OD, F and R, which are the registers that define
the ratio of the tile frequency to the oscillator frequency:
F +1 1
1
Fcor e = Fosc ×
2
××
R + 1 OD + 1







XS1-L01A-LQ64 equivalent, schematic
XS1-L01A-LQ64 Datasheet
15
6.6 Clock
Figure 13:
Clock
Symbol Parameter
MIN
f Frequency
4.22
SR Slew rate
0.10
TJ(LT)
Long term jitter (pk-pk)
f(MAX)
Processor clock frequency (Speed
Grade 4)
Processor clock frequency (Speed
Grade 5)
A Percentage of CLK period.
B Assumes typical tile and I/O voltages with nominal activity.
TYP
20
MAX
100
2
400
500
UNITS
MHz
V/ns
%
MHz
MHz
Notes
A
B
B
Further details can be found in the XS1-L Clock Frequency Control document,
X1433.
6.7 xCORE Tile I/O AC Characteristics
Figure 14:
I/O AC char-
acteristics
Symbol
T(XOVALID)
T(XOINVALID)
T(XIFMAX)
Parameter
Input data valid window
Output data invalid window
Rate at which data can be sampled
with respect to an external clock
MIN TYP MAX UNITS
8 ns
9 ns
60 MHz
Notes
The input valid window parameter relates to the capability of the device to capture
data input to the chip with respect to an external clock source. It is calculated as the
sum of the input setup time and input hold time with respect to the external clock
as measured at the pins. The output invalid window specifies the time for which
an output is invalid with respect to the external clock. Note that these parameters
are specified as a window rather than absolute numbers since the device provides
functionality to delay the incoming clock with respect to the incoming data.
Information on interfacing to high-speed synchronous interfaces can be found in
the XS1 Port I/O Timing document, X5821.
6.8 xConnect Link Performance
Figure 15:
Link
performance
Symbol
Parameter
MIN TYP MAX UNITS Notes
B(2blinkP) 2b link bandwidth (packetized)
87 MBit/s A, B
B(5blinkP) 5b link bandwidth (packetized)
217 MBit/s A, B
B(2blinkS) 2b link bandwidth (streaming)
100 MBit/s B
B(5blinkS) 5b link bandwidth (streaming)
250 MBit/s B
A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header
and payload.
B 7.5 ns symbol time.
X1135,










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