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零件编号 | MK10DN64VFM5 | ||
描述 | Microcontroller | ||
制造商 | Freescale Semiconductor | ||
LOGO | |||
1 Page
K10 Sub-Family Reference Manual
Supports: MK10DN32VFM5, MK10DX32VFM5, MK10DN64VFM5,
MK10DX64VFM5, MK10DN128VFM5, MK10DX128VFM5
Document Number: K10P32M50SF0RM
Rev. 2, Feb 2012
Section Number
Title
Page
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................169
9.1.1 References....................................................................................................................................................171
9.2 The Debug Port.............................................................................................................................................................171
9.2.1 JTAG-to-SWD change sequence.................................................................................................................172
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................172
9.3 Debug Port Pin Descriptions.........................................................................................................................................173
9.4 System TAP connection................................................................................................................................................173
9.4.1 IR Codes.......................................................................................................................................................173
9.5 JTAG status and control registers.................................................................................................................................174
9.5.1 MDM-AP Control Register..........................................................................................................................175
9.5.2 MDM-AP Status Register............................................................................................................................177
9.6 Debug Resets................................................................................................................................................................179
9.7 AHB-AP........................................................................................................................................................................179
9.8 ITM...............................................................................................................................................................................180
9.9 Core Trace Connectivity...............................................................................................................................................180
9.10 TPIU..............................................................................................................................................................................180
9.11 DWT.............................................................................................................................................................................180
9.12 Debug in Low Power Modes........................................................................................................................................181
9.12.1 Debug Module State in Low Power Modes.................................................................................................182
9.13 Debug & Security.........................................................................................................................................................182
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................183
10.2 Signal Multiplexing Integration....................................................................................................................................183
10.2.1 Port control and interrupt module features..................................................................................................184
10.2.2 PCRn reset values for port A.......................................................................................................................184
10.2.3 Clock gating.................................................................................................................................................184
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
8 Freescale Semiconductor, Inc.
Section Number
Title
Page
21.4.4 Performance.................................................................................................................................................365
21.5 Initialization/application information...........................................................................................................................369
21.5.1 eDMA initialization.....................................................................................................................................369
21.5.2 Programming errors.....................................................................................................................................371
21.5.3 Arbitration mode considerations..................................................................................................................372
21.5.4 Performing DMA transfers (examples)........................................................................................................372
21.5.5 Monitoring transfer descriptor status...........................................................................................................376
21.5.6 Channel Linking...........................................................................................................................................378
21.5.7 Dynamic programming................................................................................................................................379
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................383
22.1.1 Features........................................................................................................................................................383
22.1.2 Modes of Operation.....................................................................................................................................384
22.1.3 Block Diagram.............................................................................................................................................385
22.2 EWM Signal Descriptions............................................................................................................................................386
22.3 Memory Map/Register Definition.................................................................................................................................386
22.3.1 Control Register (EWM_CTRL).................................................................................................................386
22.3.2 Service Register (EWM_SERV)..................................................................................................................387
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................388
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................388
22.4 Functional Description..................................................................................................................................................389
22.4.1 The EWM_out Signal..................................................................................................................................389
22.4.2 The EWM_in Signal....................................................................................................................................390
22.4.3 EWM Counter..............................................................................................................................................390
22.4.4 EWM Compare Registers............................................................................................................................390
22.4.5 EWM Refresh Mechanism...........................................................................................................................391
22.4.6 EWM Interrupt.............................................................................................................................................391
K10 Sub-Family Reference Manual, Rev. 2, Feb 2012
16 Freescale Semiconductor, Inc.
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页数 | 30 页 | ||
下载 | [ MK10DN64VFM5.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
MK10DN64VFM5 | Microcontroller | Freescale Semiconductor |
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