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PDF ( 数据手册 , 数据表 ) ISL12022

零件编号 ISL12022
描述 Low Power RTC
制造商 Intersil
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ISL12022 数据手册, 描述, 功能
Low Power RTC with Battery-Backed SRAM and
Embedded Temp Compensation ±5ppm with Auto
Daylight Saving
ISL12022
The ISL12022 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brownout
indicator, single periodic or polled alarms, intelligent
battery-backup switching, Battery Reseal™ function and
128 bytes of battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically, using
parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
VBAT power, and also from VBAT to VDD power.
Applications
• Utility Meters
• POS Equipment
• Medical Devices
• Security Systems
• Vending Machines
• White Goods
• Printers and Copiers
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temperature Range
- ±5ppm Over -40°C to +85°C
• 10-bit Digital Temperature Sensor Output
- ±2°C Accuracy
• Customer Programmable Day Light Saving Time
• 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Battery Reseal™ Function to Extend Battery Shelf Life
• Automatic Backup to Battery or Super Capacitor
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor
- 2 User Programmable Levels
- Seven Selectable Voltages for Each Level
• Power Status Brownout Monitor
- Six Selectable Trip Levels, from 2.295V to 4.675V
• Oscillator Failure Detection
• Time Stamp for First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Bus™
- 400kHz Clock Frequency
• 1µA Typical Battery Current
• Pb-Free (RoHS Compliant)
VDD = 2.7V
TO 5.5V
CIN
0.1µF
ISL12022
VDD VBAT
GND
JBAT
DBAT
BAT43W
CBAT
0.1µF
+ VBAT = 1.8V
TO 3.2V
FIGURE 1. TYPICAL APPLICATION CIRCUIT
November 22, 2011
FN6659.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) and Battery Reseal are trademarks owned by Intersil Corporation or one of its subsidiaries.
I2C Bus is a trademark owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.







ISL12022 pdf, 数据表
ISL12022
Typical Performance Curves Temperature is +25°C unless otherwise specified.
1050
1600
1000
1400
950
900
850
800
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VBAT VOLTAGE (V)
FIGURE 3. IBAT vs VBAT
1200
1000
800
600
-40
VBAT = 5.5V
VBAT = 3.0V
VBAT = 1.8V
-20 0
20 40
TEMPERATURE (°C)
FIGURE 4. IBAT vs TEMPERATURE
60
80
6
5
VBAT = 5.5V
4
VBAT = 2.7V
3 VDD = 3.3V
2
-40 -20
0 20 40
TEMPERATURE (°C)
60
FIGURE 5. IDD1 vs TEMPERATURE
80
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.7
3.2 3.7 4.2
VDD (V)
FIGURE 6. IDD1 vs VDD
4.7
5.2
6
5 VDD = 5.5V
4
3 VDD = 3.3V
VDD = 2.7V
2
0.01 0.1 1 10 100 1k
FREQUENCY OUTPUT (Hz)
FIGURE 7. FOUT vs IDD
10k 100k
5.5
5.0
4.5 FOUT = 32kHz
4.0
3.5 FOUT = 1Hz and 64Hz
3.0
2.5-40
-20
0
20 40 60 80
TEMPERATURE (°C)
FIGURE 8. IDD vs TEMPERATURE, 3 DIFFERENT FOUT
8 FN6659.3
November 22, 2011







ISL12022 equivalent, schematic
ISL12022
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN (Continued)
FREQUENCY,
FOUT
4
UNITS
Hz
FO3
1
FO2 FO1 FO0
000
2
Hz 1
001
1
Hz 1
010
1/2 Hz 1 0 1 1
1/4 Hz 1 1 0 0
1/8 Hz 1 1 0 1
1/16
Hz 1
110
1/32 Hz 1
111
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
ADDR 7 6 5 4 3
2
1
0
09h CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0
This bit clears Time Stamp VDD to Battery (TSV2B) and Time
Stamp Battery to VDD Registers (TSB2V). The default setting is 0
(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
VDD Brownout Trip Voltage BITS (VDDTrip<2:0)
These bits set the 6 trip levels for the VDD alarm, indicating that
VDD has dropped below a preset level. In this event, the LVDD bit
in the Status Register is set to “1”. See Table 6.
TABLE 6. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP VOLTAGE
(V)
0 0 0 2.295
0 0 1 2.550
0 1 0 2.805
0 1 1 3.060
1 0 0 4.250
1 0 1 4.675
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
TABLE 7.
ADDR 7 6
5432
10
0Ah D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting VBAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
The application for this bit involves placing the chip on a board
with a battery and testing the board. Once the board is tested
and ready to ship, it is desirable to disconnect the battery to keep
it fresh until the board or unit is placed into final use. Setting
RESEALB = “1” initiates the battery disconnect, and after VDD
power is cycled down and up again, the RESEAL bit is cleared
to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits select the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal Battery voltage level.
See Table 8.
VB85Tp2
0
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0 0 2.125
0 0 1 2.295
0 1 0 2.550
0 1 1 2.805
1 0 0 3.060
1 0 1 4.250
1 1 0 4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal VBAT) level for
the battery voltage monitor. There are total of 7 levels that could be
selected for the second alarm. Any of the of levels could be selected
as the second alarm with no reference as to nominal Battery voltage
level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM
TRIP LEVEL
(V)
0 0 0 1.875
0 0 1 2.025
0 1 0 2.250
0 1 1 2.475
1 0 0 2.700
1 0 1 3.750
1 1 0 4.125
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room temperature)
of the crystal. Both Digital Trimming (DT) and Analog Trimming
(AT) methods are available. The digital trimming uses clock pulse
skipping and insertion for frequency adjustment. Analog
16 FN6659.3
November 22, 2011










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