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PDF ( 数据手册 , 数据表 ) ISL23345

零件编号 ISL23345
描述 Low Voltage Digitally Controlled Potentiometer
制造商 Intersil
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ISL23345 数据手册, 描述, 功能
Quad, 256 Tap, Low Voltage Digitally ControlledNORTECROEMCOMMENMDEENDIDSERLD2E3PF3LO2A5RCNEEMWENDTEPSAIGRNTS
Potentiometer (XDCP™)
ISL23345
The ISL23345 is a volatile, low voltage, low noise, low power,
256 tap, quad digitally controlled potentiometer (DCP) with an
I2C Businterface. It integrates four DCP cores, wiper switches
and control logic on a monolithic CMOS integrated circuit.
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly
written to and read by the user. The contents of the WRi
controls the position of the wiper. When powered on, the wiper
of each DCP will always commence at mid-scale (128 tap
position).
The low voltage, low power consumption, and small package
of the ISL23345 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23345 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23345 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Applications
• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
Features
• Four potentiometers per package
• 256 resistor taps
• 10k 50kor 100ktotal resistance
• I2C serial interface
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
• Maximum supply current without serial bus activity
(standby)
- 5µA @ VCC and VLOGIC = 5V
- 2µA @ VCC and VLOGIC = 1.7V
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70typical @ VCC = 3.3V
• Power-on preset to mid-scale (128 tap position)
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 QFN packages
• Pb-free (RoHS compliant)
10000
8000
6000
4000
2000
0
0 64 128 192
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kDCP
256
VREF
RH1
1 DCP
of
ISL23345
RW1
RL1
-
+
ISL28114
VREF_M
FIGURE 2. VREF ADJUSTMENT
June 21, 2011
FN7872.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners







ISL23345 pdf, 数据表
ISL23345
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted. (Continued)
SYMBOL
tDH
tR
tF
Cb
PARAMETER
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
TEST CONDITIONS
From SCL falling edge crossing 30% of VLOGIC,
until SDA enters the 30% to 70% of VLOGIC
window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA,
VLOGIC < 2V
From 30% to 70% of VLOGIC
From 70% to 30% of VLOGIC
Total on-chip and off-chip
MIN
(Note 20)
0
TYP
(Note 8)
MAX
(Note 20)
UNITS
ns
20 + 0.1 x Cb
20 + 0.1 x Cb
10
250 ns
250 ns
400 pF
tSU:A
A1, A0, A2 Setup Time
Before START condition
600
ns
tHD:A
A1, A0, A2 Hold Time
After STOP condition
600 ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255
14.
TCV
=
M------a----x-----V---V---R---R--W--W-----i-i----+-–---2-M--5---i-°-n---C----V------R----W--------i--
------1----0----6-------
+ 165 °C
for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
voltage and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
19.
TCR
=
---M-----a----x-R----R-i----i+----2-–--5---M-°----iC--n------R----i-----
------1----0----6-------
+ 165 °C
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC
first followed by the VCC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 3 and y = 0 to 3.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255, x = 0 to 3 and y = 0 to 3.
8 FN7872.0
June 21, 2011







ISL23345 equivalent, schematic
ISL23345
SCL FROM
MASTER
SDA OUTPUT FROM
TRANSMITTER
1
89
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
WRITE
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
1 0 1 0 A2A1 A0 0 0 0 0
A
C
K
A
C
K
FIGURE 29. BYTE WRITE SEQUENCE
DATA
BYTE
S
T
O
P
A
C
K
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R BYTE WITH
T R/W = 0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T R/W = 1
READ
AA
CC
KK
S
AT
CO
KP
SIGNAL AT SDA 1 0 1 0 A2A1 A0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
C
K
1 0 1 0 A2A1 A0 1
AA
C
K
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 30. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23345 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23345 responds
with an ACK; then the ISL23345 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
16 FN7872.0
June 21, 2011










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