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PDF ( 数据手册 , 数据表 ) CY14B256Q

零件编号 CY14B256Q
描述 256-Kbit (32 K x 8) SPI nvSRAM
制造商 Cypress Semiconductor
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CY14B256Q 数据手册, 描述, 功能
CY14C256Q
CY14B256Q
CY14E256Q
256-Kbit (32 K × 8) SPI nvSRAM
256-Kbit (32 K × 8) SPI nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Support automatic STORE on power-down with a small
capacitor (except for CY14X256Q1A)
High reliability
Infinite read, write, and RECALL cycles
1million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
40 MHz and 104 MHz High speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and SPI read (with special fast
read instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 150 A
Sleep mode current of 8 A
Logic Block Diagram
VCC VCAP
Industry standard configurations
Operating voltages:
• CY14C256Q: VCC = 2.4 V to 2.6 V
• CY14B256Q: VCC = 2.7 V to 3.6 V
• CY14E256Q: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X256Q combines a 256-Kbit nvSRAM[1] with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 32 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14X256Q1A). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). You can also initiate the STORE
and RECALL operations through SPI instruction.
For a complete list of related documentation, click here.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X256Q1A CY14X256Q2A CY14X256Q3A
No Yes Yes
Yes Yes Yes
No No Yes
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacturer ID /
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65282 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2014







CY14B256Q pdf, 数据表
CY14C256Q
CY14B256Q
CY14E256Q
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage.
As described earlier, at power-up nvSRAM performs a Power-Up
RECALL operation for tFA duration during which, all memory
accesses are disabled. The HSB pin can be probed to check the
Ready/Busy status of nvSRAM after power-up.
The following are the device status after power-up.
Selected (Active power mode) if CS pin is LOW
Deselected (Standby power mode) if CS pin is HIGH
Not in the Hold condition
Status Register state:
Write Enable (WEN) bit is reset to ‘0’.
WPEN, BP1, BP0 unchanged from previous STORE
operation.
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
on VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 20. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode after tSB time if a STORE or RECALL cycle is not in
progress. If a STORE/RECALL cycle is in progress, the device
goes into the standby power mode after the STORE or RECALL
cycle is completed. In the standby power mode, the current
drawn by the device drops to ISB.
Document Number: 001-65282 Rev. *I
Page 8 of 33







CY14B256Q equivalent, schematic
CY14C256Q
CY14B256Q
CY14E256Q
Special Instructions
SLEEP Instruction
SLEEP instruction puts the nvSRAM in sleep mode. When the
SLEEP instruction is issued, the nvSRAM takes tSS time to
process the SLEEP request. Once the SLEEP command is
successfully registered and processed, the nvSRAM toggles
HSB LOW, performs a STORE operation to secure the data to
nonvolatile memory and then enters into SLEEP mode. The
device starts consuming IZZ current after tSLEEP time from the
instance when SLEEP instruction is registered. The device is not
accessible for normal operations after SLEEP instruction is
issued. Once in sleep mode, the SCK and SI pins are ignored
and SO will be Hi-Z but device continues to monitor the CS pin.
To wake the nvSRAM from the sleep mode, the device must be
selected by toggling the CS pin from HIGH to LOW. The device
wakes up and is accessible for normal operations after tWAKE
duration after a falling edge of CS pin is detected.
Note Whenever nvSRAM enters into sleep mode, it initiates
nonvolatile STORE cycle which results in an endurance cycle per
sleep command execution. A STORE cycle starts only if a write
to the SRAM has been performed since the last STORE or
RECALL cycle.
Figure 21. Sleep Mode Entry
CS
SCK
tSLEEP
01234567
Serial Number
The serial number is an 8 byte programmable memory space
provided to you uniquely identify this device. It typically consists
of a two byte Customer ID, followed by five bytes of unique serial
number and one byte of CRC check. However, nvSRAM does
not calculate the CRC and it is up to the system designer to utilize
the eight byte memory space in whatever manner desired. The
default value for eight byte locations are set to ‘0x00’.
WRSN (Serial Number Write) Instruction
The serial number can be written using the WRSN instruction. To
write serial number the write must be enabled using the WREN
instruction. The WRSN instruction can be used in burst mode to
write all the 8 bytes of serial number.
The serial number is locked using the SNL bit of the Status
Register. Once this bit is set to '1', no modification to the serial
number is possible. After the SNL bit is set to '1', using the WRSN
instruction has no effect on the serial number.
A STORE operation (AutoStore or Software STORE) is required
to store the serial number in nonvolatile memory. If AutoStore is
disabled, you must perform a Software STORE operation to
secure and lock the serial Number. If SNL bit is set to ‘1’ and is
not stored (AutoStore disabled), the SNL bit and serial number
defaults to ‘0’ at the next power cycle. If SNL bit is set to ‘1’ and
is stored, the SNL bit can never be cleared to ‘0’. This instruction
requires the WEN bit to be set before it can be executed. The
WEN bit is reset to '0' after completion of this instruction.
SI 1 0 1 1 1 0 0 1
SO HI-Z
Figure 22. WRSN Instruction
CS
SCK
SI
SO
0 1 2 34 5 67 0 1 23 4 56 7
56 57 58 59 60 61 62 63
11
Op-Code
Byte - 8
Byte - 1
0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
8-Byte Serial Number
LSB
HI-Z
Document Number: 001-65282 Rev. *I
Page 16 of 33










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