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PDF ( 数据手册 , 数据表 ) S4041-1B1

零件编号 S4041-1B1
描述 3.0V e.MMC Flash
制造商 Cypress Semiconductor
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S4041-1B1 数据手册, 描述, 功能
S4041-1B1
8 GB / 16 GB, 3.0 V e.MMC Flash
Features
e.MMC 4.51 Specification compatible
Backward compatible with previous e.MMC specifications
Storage temperature
40 °C to +85 °C
Operating voltage
VCCQ: 1.7 V - 1.95 V or 2.7 V - 3.6 V
VCC: 2.7 V - 3.6 V
Density: 8/16 GB of data storage
Data bus width:
SDR mode: 1 bit, 4 bit, 8 bit
DDR mode: 4 bit, 8 bit
HS200 mode: 4 bit, 8 bit
Clock frequency: 52 MHz, 200 MHz (e.MMC 4.51)
SDR mode: up to 52 MHz
DDR mode: up to 52 MHz
HS200 mode: up to 200 MHz
BGA packages
153-ball VFBGA: 13 mm 11.5 mm 1.0 mm
100-ball LBGA: 18 mm 14 mm 1.4 mm
Operating temperature range
Embedded: 25 °C to +85 °C
Industrial: 40 °C to +85 °C
Key Supported Features
Boot Operation
Partition Management
Boot Area Partition
Replay Protected Memory Block (RPMB)
Sleep (CMD5)
Sanitize
Trim
High Priority Interrupt
Background Operations
Auto Background Operations
Hardware Reset
HS200
Health Monitoring
Performance
Sequential Read (MB/s): 120
Sequential Write (MB/s): 20
Based on 16-GB device
Bus in x8 I/O and HS200 modes
Random Read (IOPS): 5000
Random Write (IOPS): 1400
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-02760 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 03, 2016







S4041-1B1 pdf, 数据表
S4041-1B1
Table 2. Partition Type
Partition
Boot Area 1
Boot Area 2
RPMB Area
User Data Area
General Purpose Partition
Enhanced
Default
Figure 6. Partitions
General Purpose Partition
NAND Mode
SLC Mode
SLC Mode
SLC Mode
MLC or SLC Mode
SLC Mode
MLC Mode
Boot 1 Boot 2 RPMB GPA 1 GPA 2 GPA 3 GPA 3 Enhanced User Data Area (SLC mode) Default User Data Area (MLC mode)
User Data Area
Sleep (CMD5)
Sleep/Awake (CMD5) is used to switch the device between Sleep and Standby mode. During the Sleep state, VCC can be switched
off for maximum power savings. While a device is in Sleep mode it can only respond to the Reset (CMD0) and Sleep/Awake (CMD5)
commands.
High Priority Interrupt (HPI)
High Priority Interrupt (HPI) is intended to suspend an ongoing operation while allowing for a high priority read operation to be
performed.
Background Operations
e.MMC devices are equipped with a Background Operations feature (see Table 7 on page 12). When enabled, Background Operations
allow the e.MMC device to perform a number of routine data maintenance operations such as wear leveling, garbage collection, erase,
and compaction while the host CPU is not being serviced.
Auto Background Operations
Auto Background Operations is a feature that allows the e.MMC device to fully manage background operations without any require-
ments from the Host. The e.MMC device will check if background operations are required at specified intervals and initiate background
operations if needed. This frees the host from having to develop software to manage these maintenance tasks and ensure that the
e.MMC device is operating at the optimum performance levels. Issuing any command while auto background operations are occurring
will stop the current background operation activities. There will be a maximum latency of 40 ms if auto background operations are
interrupted by any read or write command from the host.
This feature is enabled on default and can be configured through the CMD56 command. A separate application note is available with
the full details of the CMD56 command. A non-disclosure agreement (NDA) is required to view this application note. Contact your
nearest Cypress sales office for more information.
Trim
Similar to the Erase operation, the Trim function (Table 7 on page 12) performs a targeted erase on specific write blocks. Data that is
no longer needed, designated by the host, will be erased during background erase events.
Sanitize
Sanitize (Table 7 on page 12) is intended for applications with high security requirements that can afford the performance impact. This
command is used in conjunction with standard Erase or Trim operations and requires the device to physically remove data from the
unmapped user address space. The busy line will be asserted once the Sanitize operations begin and will remain busy until the
operation has been completed or interrupted.
Hardware Reset
Used by the host to reset the device, hardware reset moves the device into a pre-idle state and disables the power-on period write
protection on blocks that were set at power-on as write protected.
Document Number: 002-02760 Rev. *H
Page 8 of 29







S4041-1B1 equivalent, schematic
S4041-1B1
Table 7. Extended CSD Register (EXT_CSD) (Continued)
Field Name
Field ID
Size
(Bytes)
Cell Type
Boot Write Protection Status Register BOOT_WP_STATUS
1R
Boot Area Write Protect Register
BOOT_WP
1 R/W, R/W/C_P
Reserved[8]
— 1—
User Area Write Protect Register
USER_WP
1
R/W, R/W/C_P, R/
W/E_P
Reserved[8]
— 1—
FW Configuration
FW_CONFIG
1 R/W
RPMB Size
RPMB_SIZE_MULT
1R
Write Reliability Setting Register
WR_REL_SET
1 R/W
Write Reliability Parameter Register WR_REL_PARAM
1R
Start Sanitize Operation
SANITIZE_START
1 W/E_P
Manually Start Background Opera-
tions
BKOPS_START
1 W/E_P
Enable Background Operations
Handshake
BKOPS_EN
1 R/W
Hardware Reset Function
RST_n_FUNCTION
1 R/W
HPI Management
HPI_MGMT
1 R/W/E_P
Partitioning Support
PARTITIONING_SUPPORT
1R
Max Enhanced Area Size
MAX_ENH_SIZE_MULT
3R
Partitions Attribute
PARTITIONS_ATTRIBUTE
1 R/W
Partitioning Setting
PARTITION_SETTING_COMPLETED 1
R/W
General Purpose Partition Size
GP_SIZE_MULT
12 R/W
Enhanced User Data Area Size
ENH_SIZE_MULT
3 R/W
Enhanced User Data Start Address ENH_START_ADDR
4 R/W
Reserved[8]
— 1—
Bad Block Management Mode
SEC_BAD_BLK_MGMNT
1 R/W
Production State Awareness
PRODUCTION_STATE_AWARENES
S
1
R/W/E
Package Case Temperature is
Controlled
TCASE_SUPPORT
1 W/E_P
Periodic Wakeup
PERIODIC_WAKEUP
1 R/W/E
Program CID/CSD in DDR Mode
Support
PROGRAM_CID_CSD_DDR_SUPPO
RT
1
R
Reserved[8]
— 2—
EXT_CSD
Slice
[174]
[173]
[172]
[171]
[170]
[169]
[168]
[167]
[166]
[165]
[164]
[163]
[162]
[161]
[160]
[159:157]
[156]
[155]
[154:143]
[142:140]
[139:136]
[135]
[134]
[133]
[132]
[131]
[130]
[129:128]
Value
00h
00h
00h
00h
20h
00h
05h
00h
00h
00h
00h
00h
07h
0001D2h
00h
00h
00...00h
000000h
00000000h
00h
00h
00h
00h
01h
Notes
8. Reserved bits should be read at 0, unless otherwise specified.
9. Set to 0 after power on, hardware reset or software reset selecting backward compatibility interface timings. If the host changes the value to 1, the device will operate
in high-speed mode and finally, if host changes the value to 2, HS200 interface timings will be used.
10. Set to 0 after power up and can be changed via a Switch command.
11. R = Read only.
R/W = One time programmable and readable.
R/W/E = Multiple writable with value kept after power failure, hardware reset assertion and any CMD0 reset and readable.
R/W/C_P = Writable after value cleared by power failure and hardware reset assertion (the value not cleared by CMD0 reset) and readable.
R/W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and readable.
W/E_P = Multiple writable with value reset after power failure, hardware reset assertion and any CMD0 reset and not readable.
12. Value depends on state of the device.
13. Value depends on the firmware that the device is loaded with.
Document Number: 002-02760 Rev. *H
Page 16 of 29










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