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PDF ( 数据手册 , 数据表 ) S70GL02GP

零件编号 S70GL02GP
描述 2 Gbit / 3V Page Mode S70GL-P MirrorBit Flash
制造商 Cypress Semiconductor
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S70GL02GP 数据手册, 描述, 功能
S70GL02GP
2 Gbit, 3V Page Mode
S70GL-P MirrorBit® Flash
General Description
The Cypress S70GL02GP 2 Gbit Mirrorbit Flash device is fabricated on 90-nm process technology. This device offers a fast page
access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer that allows a maximum of 32
words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard single byte/word
programming algorithms. This makes the device an ideal product for today’s embedded applications that require higher density,
better performance and lower power consumption.
This document contains information for the S70GL02GP device, which is a dual die stack of two S29GL01GP die. For detailed
specifications, refer to the discrete die datasheet provided in Table 1.
Table 1. Affected Documents/Related Documents
Title
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit
Process Technology
Publication Number
002-00886
Distinctive Characteristics
Two 1024 Mbit (S29GL01GP) in a single 64-ball Fortified-
BGA package (see S29GL01P datasheet for full
specifications)
Single 3V read/program/erase (3.0V - 3.6V)
90 nm MirrorBit process technology
8-word/16-byte page read buffer
32-word/64-byte write buffer reduces overall programming
time for multiple-word writes
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random Electronic
Serial Number
– Can be programmed and locked at the factory or by the
customer
Uniform 64Kword/128KByte Sector Architecture
– S70GL02GP: two thousand forty-eight sectors
100,000 erase cycles per sector typical
20-year data retention typical
Offered Packages
– 64-ball Fortified BGA
Suspend and Resume commands for Program and Erase
operations
Write operation status bits indicate program and erase
operation completion
Unlock Bypass Program command to reduce programming
time
Support for Common Flash Interface (CFI)
Persistent and Password methods of Advanced Sector
Protection
WP#/ACC input
– Accelerates programming time (when VACC is applied) for
greater throughput during system production
– Protects first or last sector of each die, regardless of sector
protection settings
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-01338 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 16, 2016







S70GL02GP pdf, 数据表
S70GL02GP
3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 2.
Table 2. S70GL02GP Sector & Memory Address Map
Uniform Sector Size Sector Count
64 Kword/128 Kb
2048
Sector Range
SA00
:
SA2047
Address Range (16-bit)
0000000h–000FFFFh
:
7FF0000H–7FFFFFFh
Notes
Sector Starting Address
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA001-SA2046) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the
pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 3 provides the device identification codes for the S70GL02GP. For more information on the autoselect function, refer to the
S29GL01P datasheet.
Table 3. Autoselect Addresses in System
Description
Manufacturer ID
Device ID, Word 1
Device ID, Word 2
Device ID, Word 3
Secure Device Verify
Sector Protect Verify
Address
(Base) + 00h
(Base) + 01h
(Base) + 0Eh
(Base) + 0Fh
(Base) + 03h
(SA) + 02h
Read Data (word/byte mode)
xx01h/1h
227Eh/7Eh
2248h/48h
2201h/01h
For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
xx01h/01h = Locked, xx00h/00h = Unlocked
5. Erase And Programming Performance
Table 4. Erase And Programming Performance
Parameter
Typ (Note 1) Max (Note 2) Unit
Comments
Sector Erase Time
Chip Erase Time
S70GL02GP
0.5
1024
3.5
4096
sec Excludes 00h programming
sec prior to erasure (Note 3)
Total Write Buffer Time, for 64 bytes
480
µs
Total Accelerated Write Buffer Programming Time,
for 64 bytes
432
µs
Excludes system level
overhead (Note 4)
Chip Program Time
S70GL02GP
1968
sec
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V VCC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, VCC = 3.0 V, 100,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
Document Number: 002-01338 Rev. *D
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