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PDF ( 数据手册 , 数据表 ) ADV7282

零件编号 ADV7282
描述 4x Oversampled SDTV Video Decoder
制造商 Analog Devices
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ADV7282 数据手册, 描述, 功能
Data Sheet
10-Bit, 4× Oversampled SDTV Video Decoder
with Differential Inputs and Deinterlacer
ADV7282
FEATURES
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
ADV7282: 4 analog video input channels with on-chip
antialiasing filter
ADV7282-M: 6 analog video input channels with on-chip
antialiasing filter
Video input support for CVBS (composite), Y/C (S-Video),
and YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
Short-to-battery (STB) diagnostics on 2 video inputs
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
mini-time base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive
peak white mode
Fast switching capability
Integrated interlaced-to-progressive (I2P) video output
converter (deinterlacer)
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi (Macrovision) copy protection detection
8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7282)
MIPI CSI-2 output interface (ADV7282-M only)
Full featured vertical blanking interval (VBI) data slicer
with world system teletext (WST) support
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
APPLICATIONS
Smartphone/multimedia handsets
Automotive infotainment
DVRs for video security
Media players
GENERAL DESCRIPTION
The ADV7282/ADV7282-M are versatile one-chip, multiformat
video decoders. The ADV7282/ADV7282-M automatically
detects standard analog baseband video signals compatible with
worldwide NTSC, PAL, and SECAM standards in the form of
composite, S-Video, and component video.
The ADV7282 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The ADV7282-M converts the analog video signals into an 8-bit
YCrCb 4:2:2 video data stream that is output over a mobile
industry processor interface (MIPI®) CSI-2 interface.
The analog video inputs of the ADV7282/ADV7282-M accept
single-ended, pseudo differential, and fully differential signals.
The ADV7282/ADV7282-M contain a deinterlacer (I2P con-
verter) and short to battery detection capability with two STB
diagnostic pins. The ADV7282 provides four analog inputs.
The ADV7282-M provides six analog inputs and three general-
purpose outputs.
The ADV7282/ADV7282-M are programmed via a 2-wire, serial
bidirectional port (I2C compatible) and is fabricated in a 1.8 V
CMOS process. The ADV7282/ADV7282-M are provided in
space-saving, RoHS compliant LFCSP surface-mount packages.
The ADV7282/ADV7282-M are rated over the −40°C to +105°C
temperature range. This makes the ADV7282/ADV7282-M
ideal for automotive applications.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADV7282 pdf, 数据表
Data Sheet
ADV7282
MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7282-M ONLY)
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
The CSI-2 clock lane of the ADV7282-M remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this
reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed
measurements were performed with the ADV7282-M operating in progressive mode and with a nominal 432 Mbps output data rate.
Specifications guaranteed by characterization.
Table 5.
Parameter
UNIT INTERVAL
Interlaced Output
Progressive Output
DATA LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
DATA LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
Fall Time, 85% to 15%
Rise Time, 30% to 85%
Data Lane LP Slew Rate vs. CLOAD
Maximum Slew Rate over Entire
Vertical Edge Region
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Pulse Width of LP Exclusive-OR Clock
Period of LP Exclusive-OR Clock
CLOCK LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
CLOCK LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
Fall Time, 85% to 15%
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire
Vertical Edge Region
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
DATA LANE HS TX SIGNALING
REQUIREMENTS
Low Power to High Speed Transition
Stage
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
Above 450 MHz
Symbol
UI
VOH
VOL
VOH
VOL
t9
t10
t11
|V1|
Test Conditions/Comments
Rising edge
Falling edge
Falling edge
Rising edge
Rising edge
First clock pulse after stop state or
last pulse before stop state
All other clock pulses
Rising edge
Falling edge
Falling edge
Rising edge
Rising edge
See Figure 4
Time that the D0P pin is at VOL and
the D0N pin is at VOH
Time that the D0P and D0N pins are
at VOL
t10 plus the HS-zero period
Rev. B | Page 7 of 32
Min Typ
4.63
2.31
1.1 1.2
−50 0
30
30
>0
40
20
90
1.1 1.2
−50 0
30
30
>0
50
40 + (4 × UI)
145 + (10 × UI)
140 200
150 200
Max Unit
ns
ns
1.3 V
+50 mV
25 ns
25 ns
35 ns
150 mV/ns
150 mV/ns
mV/ns
mV/ns
mV/ns
ns
ns
ns
1.3 V
+50 mV
25 ns
25 ns
150 mV/ns
150 mV/ns
mV/ns
mV/ns
mV/ns
85 + (6 × UI)
270
10
360
250
5
25
15
ns
ns
ns
mV p-p
mV
mV
mV
mV
mV
mV







ADV7282 equivalent, schematic
Data Sheet
POWER SUPPLY SEQUENCING
OPTIMAL POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7282/ADV7282-M is
to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V
supplies (DVDD, PVDD, AVDD, and MVDD). Note that MVDD only
applies to the ADV7282-M.
When powering up the ADV7282/ADV7282-M, follow these
steps. During power-up, all supplies must adhere to the
specifications listed in the Absolute Maximum Ratings section.
1. Assert the PWRDWN and RESET pins (pull the pins low).
2. Power up the DVDDIO supply.
3. After DVDDIO is fully asserted, power up the 1.8 V supplies.
4. After the 1.8 V supplies are fully asserted, pull
the PWRDWN pin high.
5. Wait 5 ms and then pull the RESET pin high.
6. After all power supplies and the PWRDWN and RESET pins
are powered up and stable, wait an additional 5 ms before
initiating I2C communication with the ADV7282-M.
SIMPLIFIED POWER-UP SEQUENCE
Alternatively, the ADV7282/ADV7282-M can be powered up
by asserting all supplies and the PWRDWN and RESET pins
simultaneously. After this operation, perform a software reset,
then wait 10 ms before initiating I2C communication with the
ADV7282/ADV7282-M.
ADV7282
While the supplies are being established, take care to ensure
that a lower rated supply does not go above a higher rated
supply level. During power-up, all supplies must adhere to the
specifications listed in the Absolute Maximum Ratings section.
POWER-DOWN SEQUENCE
The ADV7282/ADV7282-M supplies can be deasserted
simultaneously as long as DVDDIO does not go below a lower
rated supply.
DVDDIO SUPPLY VOLTAGE
For correct operation of the ADV7282-M, the DVDDIO supply
must be from 2.97 V to 3.63 V.
The ADV7282 however, can operate with a nominal DVDDIO
voltage of 1.8 V. In this case, apply the power-up sequences
described previously. The only change is that DVDDIO is powered
up to 1.8 V instead of 3.3 V, and the PWRDWN and RESET
pins of the ADV7282 are powered up to 1.8 V instead of 3.3 V.
Note that when the ADV7282 operates with a nominal DVDDIO
voltage of 1.8 V, then set the drive strength of all digital outputs
to a maximum.
Note that when DVDDIO is 1.8 V, no pin of the ADV7282 is to be
pulled up to 3.3 V. For example, the I2C pins of the ADV7282
(SCLK and SDATA) must also be pulled up to 1.8 V instead
of 3.3 V.
3.3V
3.3V SUPPLY
PWRDWN PIN
RESET PIN
1.8V
1.8V SUPPLIES
3.3V SUPPLY 1.8V SUPPLIES
POWER-UP
POWER-UP
PWRDWN PIN
POWER-UP
RESET PIN
POWER-UP
5ms
RESET
OPERATION
Figure 8. Optimal Power-Up Sequence
5ms
WAIT
TIME
Rev. B | Page 15 of 32










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