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PDF ( 数据手册 , 数据表 ) IDT70V9359L

零件编号 IDT70V9359L
描述 HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
制造商 IDT
LOGO IDT LOGO 


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IDT70V9359L 数据手册, 描述, 功能
HIGH-SPEED 3.3V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9359/49L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9359/49L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin Fine Pitch Ball Grid Array (fpBGA) packages.
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A12L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1b 0b b a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a a b0b 1b 0/1
Counter/
Address
Reg.
NOTE:
1. A12 is a NC for IDT70V9349.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A12R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5638 drw 01
©2003 Integrated Device Technology, Inc.
1
AUGUST 2003
DSC-5638/3







IDT70V9359L pdf, 数据表
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) ( VDD= 3.3V ± 0.3V, TA = 0°C to +70°C)
70V9359/49L6
Com'l Only
70V9359/49L7
Com'l & Ind
70V9359/49L9
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tCYC1
Clock Cycle Time (Flow-Through)(2)
19 ____ 22 ____ 25 ____ ns
tCYC2
Clock Cycle Time (Pipelined)(2)
10 ____ 12 ____ 15 ____ ns
tCH1 Clock High Time (Flow-Through)(2)
6.5 ____ 7.5 ____ 12 ____ ns
tCL1 Clock Low Time (Flow-Through)(2)
6.5 ____ 7.5 ____ 12 ____ ns
tCH2 Clock High Time (Pipelined)(2)
tCL2 Clock Low Time (Pipelined)(2)
4 ____ 5 ____ 6 ____ ns
4 ____ 5 ____ 6 ____ ns
tR Clock Rise Time
____ 3 ____ 3 ____ 3 ns
tF Clock Fall Time
____ 3 ____ 3 ____ 3 ns
tSA Address Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHA Address Hold Time
0 ____
0 ____
1 ____ ns
tSC Chip Enable Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHC Chip Enable Hold Time
0 ____
0 ____
1 ____ ns
tSB Byte Enable Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHB Byte Enable Hold Time
0 ____
0 ____
1 ____ ns
tSW R/W Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHW R/W Hold Time
0 ____
0 ____
1 ____ ns
tSD Input Data Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHD Input Data Hold Time
0 ____
0 ____
1 ____ ns
tSAD ADS Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHAD ADS Hold Time
0 ____
0 ____
1 ____ ns
tSCN CNTEN Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHCN CNTEN Hold Time
0 ____
0 ____
1 ____ ns
tSRST
CNTRST Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHRST
CNTRST Hold Time
0 ____
0 ____
1 ____ ns
tOE Output Enable to Data Valid
____ 6.5 ____ 7.5 ____ 9 ns
tOLZ Output Enable to Output Low-Z(1)
tOHZ Output Enable to Output High-Z(1)
2 ____
17
2 ____
17
2 ____ ns
1 7 ns
tCD1 Clock to Data Valid (Flow-Through)(2)
____ 15 ____ 18 ____ 20 ns
tCD2 Clock to Data Valid (Pipelined)(2)
____ 6.5 ____ 7.5 ____ 9 ns
tDC Data Output Hold After Clock High
2 ____ 2 ____ 2 ____ ns
tCKHZ
Clock High to Output High-Z(1)
2 9 2 9 2 9 ns
tCKLZ Clock High to Output Low-Z(1)
2 ____ 2 ____ 2 ____ ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____ 24 ____ 28 ____ 35 ns
tCCS Clock-to-Clock Setup Time
____ 9 ____ 10 ____ 15 ns
NOTES:
5638 tbl 11
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.482







IDT70V9359L equivalent, schematic
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Ordering Information
IDT XXXXX
Device
Type
A 99
Power Speed
A
Package
A
Process/
Temperature
Range
Industrial and Commercial Temperature Ranges
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BF
100-pin TQFP (PN100-1)
100-pin fpBGA (BF100)
6
7
9
Commercial Only
Commercial & Industrial Speed in nanoseconds
Commercial Only
L Low Power
70V9359 144K (8K x 18-Bit) Synchronous Dual-Port RAM
70V9349 72K (4K x 18-Bit) Synchronous Dual-Port RAM
NOTE:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
5638 drw 20
IDT Clock Solution for IDT70V9359/49 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT Dual-Port
Part Number
Voltage
I/O
Input
Capacitance
Input Duty
Cycle
Requirement
Maximum
Frequency
Jitter
Tolerance
70V9359/49
3.3
LVTTL
9pF
40%
100 150ps
IDT
PLL
Clock Device
IDT2305
IDT2308
IDT2309
IDT
Non-PLL Clock
Device
FCT3805
FCT3805D/E
FCT3807
FCT3807D/E
5638 tbl 12
Datasheet Document History
10/01/01:
7/3/02 :
08/15/03:
Initial Public Release
Page 2 & 3 Added data revision for pin configurations
Consolidated multiple devices into one datasheet
Removed Preliminary status
Page 16 Added IDT Clock Solution Table
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.1462
for Tech Support:
831-754-4613










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