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PDF ( 数据手册 , 数据表 ) IDT70V9079

零件编号 IDT70V9079
描述 HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
制造商 IDT
LOGO IDT LOGO 


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IDT70V9079 数据手册, 描述, 功能
HIGH-SPEED 3.3V
64/32K x 8 SYNCHRONOUS
Š DUAL-PORT STATIC RAM
IDT70V9089/79S/L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT70V9089/79S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9089/79L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
,
I/O0R - I/O7R
A15L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. A15X is a NC for IDT70V9079.
Counter/
Address
Reg.
©2014 Integrated Device Technology, Inc.
MEMORY
ARRAY
1
Counter/
Address
Reg.
A15R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3750 drw 01
JULY 2014
DSC 3750/12







IDT70V9079 pdf, 数据表
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3, TA = 0°C to +70°C)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tCYC1
Clock Cycle Time (Flow-Through)(2)
19 ____ 22 ____ 25 ____ ns
tCYC2
Clock Cycle Time (Pipelined)(2)
10 ____ 12 ____ 15 ____ ns
tCH1 Clock High Time (Flow-Through)(2)
6.5 ____ 7.5 ____ 12 ____ ns
tCL1 Clock Low Time (Flow-Through)(2)
6.5 ____ 7.5 ____ 12 ____ ns
tCH2 Clock High Time (Pipelined)(2)
4 ____ 5 ____ 6 ____ ns
tCL2 Clock Low Time (Pipelined)(2)
4 ____ 5 ____ 6 ____ ns
tR Clock Rise Time
____ 3 ____ 3 ____ 3 ns
tF Clock Fall Time
____ 3 ____ 3 ____ 3 ns
tSA Address Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHA Address Hold Time
0 ____ 0 ____ 1 ____ ns
tSC Chip Enable Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHC Chip Enable Hold Time
0 ____ 0 ____ 1 ____ ns
tSW R/W Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHW R/W Hold Time
0 ____ 0 ____ 1 ____ ns
tSD Input Data Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHD Input Data Hold Time
0 ____ 0 ____ 1 ____ ns
tSAD ADS Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHAD ADS Hold Time
0 ____ 0 ____ 1 ____ ns
tSCN CNTEN Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHCN CNTEN Hold Time
0 ____ 0 ____ 1 ____ ns
tSRST
CNTRST Setup Time
3.5 ____ 4 ____ 4 ____ ns
tHRST
CNTRST Hold Time
0 ____ 0 ____ 1 ____ ns
tOE Output Enable to Data Valid
____ 6.5 ____ 7.5 ____ 9 ns
tOLZ Output Enable to Output Low-Z(1)
2 ____ 2 ____ 2 ____ ns
tOHZ Output Enable to Output High-Z(1)
17
17
1 7 ns
tCD1 Clock to Data Valid (Flow-Through)(2)
____ 15 ____ 18 ____ 20 ns
tCD2 Clock to Data Valid (Pipelined)(2)
____ 6.5 ____ 7.5 ____ 9 ns
tDC Data Output Hold After Clock High
2 ____ 2 ____ 2 ____ ns
tCKHZ
Clock High to Output High-Z(1)
2 9 2 9 2 9 ns
tCKLZ Clock High to Output Low-Z(1)
2 ____ 2 ____ 2 ____ ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____ 24 ____ 28 ____ 35 ns
tCCS Clock-to-Clock Setup Time
____ 9 ____ 10 ____ 15 ns
3750 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.482







IDT70V9079 equivalent, schematic
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
INTERNAL(3)
ADDRESS
ADS
tSAD tHAD
An(7)
An + 1
An + 2
An + 3
An + 4
CNTEN
DATAIN
tSD tHD
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
3750 drw 16
CLK
ADDRESS
tSA tHA
An
(4)
An + 1
An + 2
INTERNAL(3)
ADDRESS
Ax (6)
R/W
tSW tHW
0
1 An An + 1
ADS
CNTEN
tSRST tHRST
tSAD tHAD
tSCN tHCN
CNTRST
tSD tHD
DATAIN
(5)
D0
DATAOUT
Q0 Q1 Qn
(6)
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
READ
ADDRESS n ADDRESS n+1
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
3750 drw 17
2. CE0 = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here simply
for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ address is written to during this cycle.
6.1462










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