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PDF ( 数据手册 , 数据表 ) IDT70V7339S

零件编号 IDT70V7339S
描述 HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
制造商 IDT
LOGO IDT LOGO 


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IDT70V7339S 数据手册, 描述, 功能
HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
IDT70V7339S
Features:
512K x 18 Synchronous Bank-Switchable Dual-ported SRAM
Architecture
64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus match-
ing compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on each
port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
I/O0L-17L
I/O
CONTROL
A12L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. TheBank-Switchabledual-portusesatrueSRAMcore
instead of the traditional dual-port SRAM core. As a result, it
has unique operating characteristics. Please refer to the
functionaldescriptiononpage18fordetails.
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
TMS
TCK
TRST
©2015 Integrated Device Technology, Inc.
1
CONTROL
LOGIC
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O
CONTROL
I/O0R-17R
ADDRESS
DECODE
BANK
DECODE
A12R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5628 drw 01
,
AUGUST 2015
DSC 5628/10







IDT70V7339S pdf, 数据表
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV)
70V7339S200(7)
Com'l Only
70V7339S166(6)
Com'l
& Ind
Symbol
Parameter
Test Condition
Version Typ.(4) Max. Typ.(4) Max.
70V7339S133
Com'l
& Ind
Typ.(4) Max.
Unit
IDD Dynamic Operating
Current (Both
Ports Active)
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
CEL = CER = VIH
f = fMAX(1)
COM'L S 815 950 675 790 550 645 mA
IND S ____ ____ 675 830 550 675
COM'L S 340 410 275 340 250 295 mA
IND S ____ ____ 275 355 250 310
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(3)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L S 690 770 515 640 460 520 mA
IND S ____ ____ 515 660 460 545
ISB3 Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and CER > VDDQ - 0.2V,
VIN > VDDQ - 0.2V or VIN < 0.2V,
f = 0(2)
COM'L S 10 30 10 30 10 30 mA
IND S ____ ____ 10 40 10 40
ISB4 Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
f = fMAX(1)
COM'L S 690 770 515 640 460 520 mA
IND S ____ ____ 515 660 460 545
5628 tbl 09
NOTES:
1. Atf=fMAX,addressandcontrollines(exceptOutputEnable)arecyclingatthemaximumfrequencyclockcycleof1/tCYC,using"ACTESTCONDITIONS"atinputlevelsofGNDto3V.
2. f=0meansnoaddress,clock,orcontrollineschange.AppliesonlytoinputatCMOSlevelstandby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDDDC(f=0)= 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 166MHzIndustrialTemperaturenotavailableinBF-208package.
7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade is available in BC-256 only.
6.482







IDT70V7339S equivalent, schematic
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS
An
ADS
tSAD tHAD
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT Qx - 1(2)
Qx
READ
EXTERNAL
ADDRESS
Qn Qn + 1
tDC
READ WITH COUNTER
COUNTER
HOLD
Qn + 2(2)
Qn + 3
READ
WITH
COUNTER
5628 drw 16
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
ADDRESS
An
ADS
tSAD tHAD
CNTEN
DATAOUT
tCD1
Qx(2)
tDC
READ
EXTERNAL
ADDRESS
Qn
tSAD tHAD
tSCN tHCN
Qn + 1
Qn + 2
READ WITH COUNTER
Qn + 3(2)
COUNTER
HOLD
Qn + 4
READ
WITH
COUNTER
5628 drw 17
NOTES:
1. CE0, OE, UB/LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN= VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
constant for subsequent clocks.
thedataoutputremains
6.4126










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