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PDF ( 数据手册 , 数据表 ) IDT70T3319S

零件编号 IDT70T3319S
描述 HIGH-SPEED 2.5V 512/256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM
制造商 IDT
LOGO IDT LOGO 


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IDT70T3319S 数据手册, 描述, 功能
HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UBL
LBL
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
ab
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Dout9-17_R
1b 0b
b
1a 0a
a
1/0
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
512/256/128K x 18
MEMORY
ARRAY
0a 1a 0b
1b
ba
0/1
FT/PIPER
,
I/O0L - I/O17L
Din_L
Din_R
I/O0R - I/O17R
CLKL
A18L(1)
A0L
REPEATL
ADSL
CNTENL
COL L
INTL
Counter/
Address
Reg.
CE 0 L
CE 1L
R/W L
ADDR_L
ADDR_R
INTERRUPT
COLLISION
DETECTION
LOGIC
ZZL(2)
ZZ
CO NTRO L
LOGIC
Counter/
Address
Reg.
R/WR
CE0 R
CE1R
ZZR(2)
CLKR
A18R(1)
A0R
REPEATR
ADSR
CNTENR
TDI
TDO
COLR
INTR
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2015 Integrated Device Technology, Inc.
1
,
TCK
JTAG TMS
TRST
5652 drw 01
JUNE 2015
DSC-5652/8







IDT70T3319S pdf, 数据表
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
V
VTERM(2)
(VDDQ)
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
oC
TSTG
Storage Temperature
-65 to +150
oC
TJN
Junction Temperature
+150
oC
IOUT(For VDDQ = 3.3V) DC Output Current
50 mA
IOUT(For VDDQ = 2.5V) DC Output Current
40 mA
NOTES:
5652 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, f = 1.0MHz) PQFP ONLY
Symbol
Parameter
Conditions(2) Max.
Unit
CIN Input Capacitance
VIN = 3dV
8 pF
COUT(3) Output Capacitance
VOUT = 3dV
10.5 pF
NOTES:
5652 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
VOH (3.3V)
VOL (2.5V)
VOH (2.5V)
Parameter
Input Leakage Current(1)
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
Output Low Voltage(1)
Output High Voltage(1)
Output Low Voltage(1)
Output High Voltage(1)
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
VDD = Max., VIN = 0V to VDD
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
IOL = +4mA, VDDQ = Min.
IOH = -4mA, VDDQ = Min.
IOL = +2mA, VDDQ = Min.
IOH = -2mA, VDDQ = Min.
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.482
70T3339/19/99S
Min. Max.
___ 10
___ ±30
___ 10
___ 0.4
2.4 ___
___ 0.4
2.0 ___
Unit
µA
µA
µA
V
V
V
V
5652 tbl 08







IDT70T3319S equivalent, schematic
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(3)
ADDRESS
An
tSA tHA
An +1
DATAIN
DATAOUT
(1)
tCD1
tCD1
Qn
READ
tDC
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
tCD1
tCD1
Qn + 1
tCKHZ
NOP(4)
WRITE
Qn + 3
tCKLZ
tDC
READ
,
5652 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
ADDRESS(3)
DATAIN
DATAOUT
An
tSA tHA
tCD1
(1)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ
An + 3
Dn + 3
An + 4
An + 5
tOE
tCD1
tCKLZ
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5652 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
6.1462










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