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PDF ( 数据手册 , 数据表 ) ST92195D5

零件编号 ST92195D5
描述 48-96 Kbyte ROM HCMOS MCU
制造商 STMicroelectronics
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ST92195D5 数据手册, 描述, 功能
ST92195 ST92T195 ST92E195
48-96 Kbyte ROM HCMOS MCU WITH
ON-SCREEN DISPLAY AND TELETEXT DATA SLICER
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0°C to +70°C operating temperature range
s Up to 24 MHz. operation @ 5V±10%
s Min. instruction cycle time: 165ns at 24 MHz.
s 48, 56, 64, 84 or 96 Kbytes ROM
s 256 bytes RAM of Register file (accumulators or
index registers)
s 256 to 512 bytes of on-chip static RAM
)s 2 or 8 Kbytes of TDSRAM (Teletext and Display
t(sStorage RAM)
cs 28 fully programmable I/O pins
us Serial Peripheral Interface
rods Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
Pfrequency external crystal.
tes Enhanced display controller with 26 rows of
40/80 characters
ole– 2 sets of 512 characters
s– Serial and Parallel attributes
b– 10x10 dot matrix, definable by user
- O– 4/3 and 16/9 supported in 50/60Hz and 100/
)120 Hz mode
t(s– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
cintensity color, translucency and half-tone
dumodes
ros Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
Ps VPS and Wide Screen Signalling slicer
tes Integrated Sync Extractor and Sync Controller
les 14-bit Voltage Synthesis for tuning reference
ovoltage
bss Up to 6 external interrupts plus one Non-
Maskable Interrupt
Os 8 x 8-bit programmable PWM outputs with 5V
PSDIP56
TQFP64
See end of Datasheet for ordering information
s I²C Master/Slave (on some devices)
s 4-channel A/D converter; 5-bit guaranteed
s Rich instruction set and 14 addressing modes
s Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
s Pin-compatible EPROM and OTP devices
available
Device Summary
Device ROM RAM TDSRAM I²C Timer
ST92195C3
256 2K
ST92195C4 48K
6K
ST92195C5
ST92195C6 56K
No 1
512
ST92195C7 64K
8K
open-drain or push-pull capability
ST92195C8 84K
s 16-bit watchdog timer with 8-bit prescaler
ST92195C9 96K
s 1 or 2 16-bit standard timer(s) with 8-bit
ST92195D5 48K
prescaler
ST92195D6 56K 512
8K Yes 2
ST92195D7 64K
October 2003
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ST92195D5 pdf, 数据表
ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
cy programmable via the CCU. In this mode, the
The ST92195C and ST92195D microcontrollers
are developed and manufactured by STMicroelec-
tronics using a proprietary n-well HCMOS proc-
ess. Their performance derives from the use of a
flexible 256-register programming model for ultra-
fast context switching and real-time event re-
sponse. The intelligent on-chip peripherals offload
the ST9 core from I/O and data management
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
processing tasks allowing critical application tasks 1.1.3 I/O Ports
to get the maximum use of core resources. The
ST92195C/D MCU support low power consump-
tion and low voltage operation for power-efficient
and low-cost embedded systems.
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
1.1.1 ST9+ Core
)The advanced Core consists of the Central
t(sProcessing Unit (CPU), the Register File and the
Interrupt controller.
ucThe general-purpose registers can be used as ac-
dcumulators, index registers, or address pointers.
roAdjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
Phas an 8-bit ALU, the chip handles 16-bit opera-
tetions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
oleTwo basic addressable spaces are available: the
sMemory space and the Register File, which in-
bcludes the control and status registers of the on-
Ochip peripherals.
-1.1.2 Power Saving Modes
t(s)To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
ccally selected.
uRun Mode. This is the full speed execution mode
dwith CPU and peripherals running at the maximum
roclock speed delivered by the Phase Locked Loop
P(PLL) of the Clock Control Unit (CCU).
teWait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
letil an interrupt request is acknowledged. During
oWFI, the CPU clock is halted while the peripherals
Obsand interrupt controller keep running at a frequen-
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM of two 512-char-
acter sets. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
can be used to store Teletext pages as well as Dis-
play parameters.
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ST92195D5 equivalent, schematic
ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Port
Name
General
Pin No.
Purpose I/O TQFP64 SDIP56
Alternate Functions
P4.4
PWM4
O PWM Output 4
44 46
SCL2
I/O I²C Channel 2 Serial Clock 1)
P4.5
PWM5
O PWM Output 5
45
47
SDA2
I/O I²C Channel 2 Serial Data 1)
P4.6
P4.7
All ports useable
for general pur-
pose I/O (input,
output or bidi-
rectional)
46
47
48 PWM6
EXTRG
49 PWM7
STOUT0
INT2
O PWM Output 6
I A/D Converter External Trigger Input
O PWM Output 7
O Standard Timer 0 Output
I External Interrupt 2
P5.0
14 20 SCK
SCL1
O SPI Serial Clock
I/O I²C Channel 1 Serial Clock 1)
SDO
O SPI Serial Data Out
P5.1
13 19 SDI
I SPI Serial Data In
SDA1
I/O I²C Channel 1 Serial Data 1)
t(s)Note 1: I²C available on ST92195D devices only.
cTable 2. I/O Port Styles
uPins
Weak Pull-Up
Port Style
Reset Values
rodP0[7:0]
no
Standard I/O
BID / OD / TTL
P2[5,4,3,2]
no
Standard I/O
BID / OD / TTL
PP2[1,0]
no
Schmitt trigger
BID / OD / TTL
teP3.7
yes
Standard I/O
AF / PP / TTL
leP3[6,5,4]
no
Standard I/O
BID / OD / TTL
oP4[7:0]
no
Standard I/O
BID / OD / TTL
sP5[1:0]
no
Standard I/O
BID / OD / TTL
bLegend:
OAF= Alternate Function, BID = Bidirectional, OD = Open Drain
-PP = Push-Pull, TTL = TTL Standard Input Levels
t(s)How to Read this Table
cTo configure the I/O ports, use the information in
duthis table and the Port Bit Configuration Table in
rothe I/O Ports Chapter on page 71.
– If WPU = yes, then the WPU can be enabled/dis-
able by software
– If WPU = no, then enabling the WPU by software
has no effect
PPort Style= the hardware characteristics fixed for
teeach port line.
leInputs:
so– If port style = Standard I/O, either TTL or CMOS
binput level can be selected by software.
O– If port style = Schmitt trigger, selecting CMOS or
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corre-
TTL input by software has no effect, the input will
sponding peripheral. Exception to this are ADC
always be Schmitt Trigger.
analog inputs which must be explicitly selected
Weak Pull-Up = This column indicates if a weak
as AF by software.
pull-up is present or not.
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