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PDF ( 数据手册 , 数据表 ) FDC37B787

零件编号 FDC37B787
描述 Super I/O Controller
制造商 SMSC Corporation
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FDC37B787 数据手册, 描述, 功能
FDC37B78x
Super I/O Controller with ACPI Support,
Real Time Clock and Consumer IR
FEATURES
ƒ 5 Volt Operation
ƒ PC98/99 and ACPI 1.0 Compliant
ƒ Battery Back-up for Wake-Events
ƒ ISA Plug-and-Play Compatible Register Set
- 12 IRQ Options
- 15 Serial IRQ Options
- 16 Bit Address Qualification
- Four DMA Options
- 12mA AT Bus Drivers
ƒ BIOS Buffer
ƒ 20 GPI/O Pins
ƒ 32KHz Standby Clock Output
ƒ Soft Power Management
ƒ ACPI/PME Support
ƒ SCI/SMI Support
- Watchdog timer
- Power Button Override Event
- Either Edge Triggered Interrupts
ƒ Intelligent Auto Power Management
- Shadowed Write-only Registers
- Programmable Wake-up Event Interface
ƒ 8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
ƒ Real Time Clock
- Day of Month Alarm, Century Byte
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 5μA Standby Battery Current (max)1
ƒ 2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
- Supports Two Floppy Drives Directly
- Software Write Protect
- FDC on Parallel Port
- Low Power CMOS Design
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun
Conditions
- 24mA Drivers and Schmitt Trigger
Inputs
ƒ Enhanced FDC Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation
Modes
1







FDC37B787 pdf, 数据表
DESCRIPTION OF PIN FUNCTIONS
PIN
No./QFP
44-47,
49-52
23-38
43
64
53
40
39
55
57
59
61
54
56
58
60
63
41
42
22
66
68
18
62, 93,
121
NAME
TOTAL SYMBOL
PROCESSOR/HOST INTERFACE (40)
System Data Bus
8 SD[0:7]
16-bit System Address Bus
Address Enable
I/O Channel Ready
ISA Reset Drive
Serial IRQ/IRQ15
PCI Clock/IRQ14/GP50
DMA Request 0
DMA Request 1
DMA Request 2
DMA Request 3
DMA Acknowledge 0
DMA Acknowledge 1
DMA Acknowledge 2
DMA Acknowledge 3
Terminal Count
I/O Read
I/O Write
14.318MHz Clock Input
32.768kHz Crystal Input
32.768kHz Crystal Driver
32.768kHz Clock Out
+5V Supply Voltage
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CLOCKS (4)
1
1
1
1
POWER PINS (10)
3
SA[0:15]
AEN
IOCHRDY
RESET_DRV
SER_IRQ
PCI_CLK
DRQ0
DRQ1
DRQ2
DRQ3
nDACK0
nDACK1
nDACK2
nDACK3
TC
nIOR
nIOW
CLOCKI
XTAL1
XTAL2
CLK32OUT
VCC
BUFFER TYPE
IO12
I
I
OD12
IS
IO12
IO12
O12
O12
O12
O12
I
I
I
I
I
I
I
I
ICLK
OCLK
O8
7







FDC37B787 equivalent, schematic
FLOPPY DISK CONTROLLER
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and the
floppy disk drives. The FDC integrates the
functions of the Formatter/Controller, Digital Data
Separator, Write Precompensation and Data Rate
Selection logic for an IBM XT/AT compatible FDC.
The true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
The FDC is compatible to the 82077AA using
SMSC's proprietary floppy disk controller core.
FDC INTERNAL REGISTERS
The Floppy Disk Controller contains eight internal
registers that facilitate the interfacing between the
host microprocessor and the disk drive. TABLE 4
shows the addresses required to access these
registers. Registers other than the ones shown are
not supported. The rest of the description
assumes that the primary addresses have been
selected.
TABLE 4 - STATUS, DATA AND CONTROL REGISTERS
(Shown with base addresses of 3F0 and 370)
PRIMARY
SECONDARY
ADDRESS
ADDRESS
R/W
REGISTER
3F0 370 R Status Register A (SRA)
3F1 371 R Status Register B (SRB)
3F2 372 R/W Digital Output Register (DOR)
3F3 373 R/W Tape Drive Register (TSR)
3F4 374 R Main Status Register (MSR)
3F4 374 W Data Rate Select Register (DSR)
3F5 375 R/W Data (FIFO)
3F6 376
Reserved
3F7 377 R Digital Input Register (DIR)
3F7 377 W Configuration Control Register (CCR)
16










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