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PDF ( 数据手册 , 数据表 ) RK616

零件编号 RK616
描述 partner chip for Rockchip mobile application processor
制造商 Rockchip
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RK616 数据手册, 描述, 功能
RK61X Technical Reference ManualRev 1.3.1
RK61X
Technical Reference Manual
Revision1.3.1
Mar. 2013
High Performance and Low-power Processor for Digital Media Application
1







RK616 pdf, 数据表
RK61X Technical Reference ManualRev 1.3.1
Figure Index
Fig. 1-1RK61X Block Diagram .............................................................. 15
Fig. 1-2 RK616 TFBGA(HF) Package Top View ......................................... 23
Fig. 1-3 RK616 TFBGA(HF) Package Side View........................................ 24
Fig. 1-4 RK616 TFBGA(HF) Package Bottom View.................................... 24
Fig. 1-5 RK616 TFBGA(HF) Package Dimension....................................... 24
Fig. 1-6 RK618 TFBGA(HF) Package Top View ......................................... 25
Fig. 1-7 RK618 TFBGA(HF) Package Side View........................................ 25
Fig. 1-8 RK618 TFBGA(HF) Package Bottom View.................................... 26
Fig. 1-9 RK618 TFBGA(HF) Package Dimension....................................... 26
Fig. 1-10 RK616 Ball Mapping Diagram.................................................. 27
Fig. 1-11 RK618 Ball Mapping Diagram.................................................. 27
Fig. 1-12PCB Scheme for TMDS Channel................................................ 29
Fig. 1-13PCB Scheme for DDC Channel ................................................. 30
Fig. 1-14PCB Scheme for hpd .............................................................. 30
Fig. 1-15PCB Scheme for ESD .............................................................. 31
Fig. 1-16PCB Scheme for CODEC.......................................................... 31
Fig. 2-1 I2C Block Diagram .................................................................. 33
Fig. 2-2I2C WritingOperation ............................................................... 33
Fig.2-3I2C Reading Operation .............................................................. 33
Fig.2-4I2C Glitch Filter Waveform ......................................................... 34
Fig. 2-5 I2C timing diagram ................................................................. 62
Fig. 2-6I2C Flow chat for tx only mode .................................................. 64
Fig. 2-7I2C Flow chat for mix mode ...................................................... 65
Fig. 3-1Chip Clock Architecture Diagram 1 ............................................. 67
Fig. 3-2Reset Architecture Diagram....................................................... 68
Fig. 3-3PLL Block Diagram ................................................................... 69
Fig. 4-1Block diagram of VIF ................................................................ 71
Fig. 4-2 LCDC RGB interface timing (SDR) ............................................. 72
Fig. 4-3 LCDC RGB interface timing (DDR) ............................................. 73
Fig. 4-2 VIF Frame Sync...................................................................... 75
Fig. 4-3 VIF Input/output Active frame period ........................................ 76
Fig. 4-4 VIF frame scanning start point.................................................. 77
Fig. 5-1Block diagram of SCALER.......................................................... 78
Fig. 5-2 SCALER Output Timing setting.................................................. 80
Fig. 5-3 SCALER Frame Sync ............................................................... 81
Fig. 5-4 SCALER Input/output Active frame period .................................. 82
Fig. 5-5 SCALER frame scanning start point ........................................... 83
Fig. 6-1Block diagram of DITHER.......................................................... 84
Fig. 7-1MIPI Controller architecture ...................................................... 86
Fig. 7-224 bpp APB Pixel to Byte Organization ........................................ 89
Fig. 7-318 bpp APB Pixel to Byte Organization ........................................ 90
Fig. 7-416 bpp APB Pixel to Byte Organization ........................................ 90
Fig. 7-512 bpp APB Pixel to Byte Organization ........................................ 90
Fig. 7-68 bpp APB Pixel to Byte Organization.......................................... 90
Fig. 7-7Command Transmission Periods within the Image Area ................. 91
Fig. 7-8Location of outvact_lpcmd_time and invact_lpcmd_time in the Image
Area ........................................................................................... 93
Fig. 8-1MIPI D-PHY simplified Block diagram with master to slave ............118
Fig. 8-2MIPI D-PHY V1.0 detailed block diagram ....................................119
Fig. 8-3HS-TX PPI Timing ...................................................................154
Fig. 8-4LPDT TX PPI Timing ................................................................154
Fig. 8-5LPDT RX PPI Timing ................................................................155
High Performance and Low-power Processor for Digital Media Application
8







RK616 equivalent, schematic
RK61X Technical Reference ManualRev 1.3.1
VCC
G5,J6
N/A 3.3 N/A
Digital IO Power
VDD
F5,F8,H7,D10
N/A 1.2 N/A
Internal Core Power
LVDS_VCC
A11,A12,B11,
E10,F10
N/A 2.5 N/A
LVDS Analog power
PLL1VDD_1V2
J10
N/A 1.2 N/A
PLL1 1.2 power
PLL2VDD_1V2
K10
N/A 1.2 N/A
PLL2 1.2 power
PLL1VDD_3V3
K10
N/A 3.3 N/A
PLL1 3.3 power
PLLVSS
K11
N/A N/A N/A
PLL analog ground
AVCC
C4,C7
A7,B8,B9
HDMI 3.3 analog power
N/A 3.3 N/A
CODEC Analog power
HDMIVDD D6 N/A 1.2 N/A HDMI 1.2 analog power
High Performance and Low-power Processor for Digital Media Application
16










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