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PDF ( 数据手册 , 数据表 ) 849S625

零件编号 849S625
描述 Crystal-to-LVPECL/LVDS Clock Synthesizer
制造商 IDT
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849S625 数据手册, 描述, 功能
Crystal-to-LVPECL/LVDS
Clock Synthesizer
849S625
Data Sheet
General Description
Features
The 849S625 is a high frequency clock generator. The 849S625
uses an external 25MHz crystal to synthesize 625MHz, 312.5MHz,
156.25MHz and 125MHz clocks. The 849S625 has excellent
cycle-to-cycle and RMS phase jitter performance.
The 849S625 operates at full 3.3V supply mode and is available in a
fully RoHS compliant 48-lead TQFP, E-Pad package.
Frequency Table for Bank A, B and C Outputs
Ten selectable differential LVPECL or LVDS outputs
Output frequencies of 625MHz, 312.5MHz, 156.25MHz or
125MHz using a 25MHz crystal.
Crystal interface designed for a 25MHz, parallel resonant crystal
Cycle-to-cycle jitter: 25ps (maximum)
RMS phase jitter at 156.25MHz (1MHz - 20MHz):
0.375ps (typical), LVDS outputs
Output duty cycle: 53% (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Crystal Frequency (MHz) M Feedback Divider VCO Frequency (MHz) Nx Output Divider
Output Frequency (MHz)
25
25 625
1
625
25
25 625
2
312.5
25
25 625
4
156.25
25
25 625
5
125
Pin Assignment
XTAL_IN
XTAL_OUT
VEE
SELC0
SELC1
OEA
VCC
OEB
OEC
SELB0
SELB1
VEE
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 ICS849S625I 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
QA1
nQA1
QA2
nQA2
VCCO
VEE
QA3
nQA3
QA4
nQA4
QA5
nQA5
48 Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc
1
December 2, 2015







849S625 pdf, 数据表
849S625 Data Sheet
Typical Phase Noise at 156.25MHz (LVPECL)
156.25MHz
RMS Phase Jitter (Random)
1MHz to 20MHz = 0.373ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (LVPECL)
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.694ps (typical)
©2015 Integrated Device Technology, Inc
Offset Frequency (Hz)
8
December 2, 2015







849S625 equivalent, schematic
849S625 Data Sheet
Application Schematic Example
Figure 5 shows an example of 849S625 application schematic. In this example, the device is operated at VCC = VCCA = VCCO = 3.3V. An 18pF
parallel resonant 25MHz crystal is used. The load capacitance C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. Depending
on the parasitics of the printed circuit board layout, these values might required slight adjustment to optimize the frequency accuracy. Crystals
with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are
required for proper operation.
As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply
isolation is required. The 849S625 provides separate power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of
the PCB and the other components can be placed on the opposite side.
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter
performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific
frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and
if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk
capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables
in the datasheet to ensure the logic control inputs are properly set.
 
VCC O
VCC
VCC
C1
0.01u
C2
0. 01u
C3
0.01u
C4
0.01u
C5
0. 01u
C6
0.01u
C7
0.01u
R 2 10
VCC A
C 11
10uF
C 10
0. 01u
U1
Tuning
capacitor
required
C1
27pF
C2
27pF
X1
S E LA0
S E LA1
S E LB0
S E LB1
SELC0
SELC1
O EA
O EB
O EC
41
42 SELA0
S E LA1
10
11 SELB0
S E LB1
4
5 SELC0
SELC1
6
8 O EA
9 O EB
O EC
CL =1 8p F
25MHz
1
XTA L_IN
2
XTAL_OU T
I CS849S625I
SEL_O UT
nR ESET
PLL_BY PASS
QA0
nQ A0
QA1
nQ A1
QA2
nQ A2
QA3
nQ A3
QA4
nQ A4
QA5
nQ A5
QB0
nQ B0
QB1
nQ B1
QC 0
nQC 0
QC 1
nQC 1
39
38
36
35
34
33
30
29
28
27
26
25
23
22
21
20
17
16
15
14
QA0
nQ A
QA1
nQ A1
QA2
nQ A2
QA3
nQ A3
QA4
nQ A4
QA5
nQ A5
QB0
nQ B0
QB1
nQ B1
Q C0
nQ C0
Q C1
nQ C1
R7 1K
Logic Control Input Examples
Set Logic
Set Logic
VC C
VCC
Input to '1'
Input to '0'
R U1
1K
R U2
N ot Install
3.3V
BLM18BB221SN 1
12
C 12
0. 1uF
Fer rite Bead
C13
VCC
C14
10uF
0.1uF
To Logic
Input
pins
R D1
N ot I nstall
To Logic
Input
pins
R D2
1K
3.3V
BLM18BB221SN 2
1 2 VC CO
C 15
0. 1uF
Fer rite Bead
C16 C17
10uF
0.1uF
Z o_dif f = 100 ohm
R1
100
LVDS
Term in ation
+
-
3. 3V
R3
133
Zo = 50 Ohm
R4
133
+
Zo = 50 Ohm
-
LVPECL
R5
Termination 82.5
R6
82.5
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
Op ti on al
Y-Term in ati on
+
-
R 8 R9
50 50
R 10
50
Figure 5. 849S625 Application Schematic
©2015 Integrated Device Technology, Inc
16
December 2, 2015










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