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零件编号 | P320HVN02.1 | ||
描述 | Color TFT-LCD | ||
制造商 | AUO | ||
LOGO | |||
1 Page
P320HVN02.1 Product Specification
Rev. 0.0
Model Name: P320HVN02.1
Issue Date: 2015/03/05
(*)Preliminary Specifications
( )Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
Kelly Kao
____________________________________
Note
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Alex HM Chen
____________________________________
Prepared By PM
Bryan Chu
____________________________________
© Copyright AU Optronics Corp. 2014 All Rights Reserved.
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LVDS -
V ICM
LVDS +
GND
0V
P320HVN02.1 Product Specification
Rev. 0.0
VTH
V TL
|V ID |
|V ID|
|V ID|
5. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
Fclk_ss(max)
1/FSS
Fclk
Fclk_ss(min)
© Copyright AU Optronics Corp. 2014 All Rights Reserved.
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3.6 Power Sequence for LCD
P320HVN02.1 Product Specification
Rev. 0.0
Parameter
Values
Unit
Min.
Type.
Max.
t1 0.4 --- 30 ms
t2 0.1 --- 50 ms
t3
450 ---
--- ms
t4 0*1 --- --- ms
t5 0 --- --- ms
t6 --- --- ---*2 ms
t7
500 ---
--- ms
t8
10*3 ---
50 ms
t9 0 --- --- ms
Note:
(1) t4=0 : concern for residual pattern before BLU turn off.
(2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value)
(3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be
negligible.
© Copyright AU Optronics Corp. 2014 All Rights Reserved.
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页数 | 30 页 | ||
下载 | [ P320HVN02.1.PDF 数据手册 ] |
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