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PDF ( 数据手册 , 数据表 ) AD9164

零件编号 AD9164
描述 RF DAC and Direct Digital Synthesizer
制造商 Analog Devices
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AD9164 数据手册, 描述, 功能
Data Sheet
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
FEATURES
fast hop modes, phase coherent fast frequency hopping (FFH) is
DAC update rate up to 12 GSPS (minimum)
enabled, with several modes to support multiple applications.
Direct RF synthesis at 6 GSPS (minimum)
In baseband mode, wide analog bandwidth capability combines
DC to 2.5 GHz in baseband mode
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
ture compliance from the minimum of one carrier up to the full
1.5 GHz to 7.5 GHz in Mix-Mode
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
Bypassable interpolation
interpolator filter (FIR85) enables the AD9164 to be configured
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
for lower data rates and converter clocking to reduce the overall
Excellent dynamic performance
system power and ease the filtering requirements. In Mix-Mode™
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
operation, the AD9164 can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The AD9164 data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of
all registers. The AD9164 is offered in an 165-ball, 8 mm × 8 mm,
The AD91641 is a high performance, 16-bit digital-to-analog
0.5 mm pitch CSP_BGA package, and an 169-ball, 11 mm × 11 mm,
converter (DAC) and direct digital synthesizer (DDS) that
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator. When
combined with a 100 MHz serial peripheral interface (SPI) and
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9164
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD9164 pdf, 数据表
Data Sheet
AD9164
JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
SERIAL INTERFACE SPEED
Half Rate
Full Rate
Oversampling
2× Oversampling
Test Conditions/Comments
Guaranteed operating range
Min
6
3
1.5
0.750
Typ Max
12.5
6.25
3.125
1.5625
Unit
Gbps
Gbps
Gbps
Gbps
SYSREF± TO DAC CLOCK TIMING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 6.
Parameter1
SYSREF± (AD9164BBCZ ONLY)
SYSREF± Differential Swing = 0.4 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
SYSREF± Differential Swing = 0.8 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
SYSREF± Differential Swing = 1.0 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
SYSREF± (AD9164BBCAZ ONLY)
SYSREF± Differential Swing = 1.0 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
Test Conditions/Comments
DC-coupled, common-mode voltage = 1.2 V
Min Typ Max Unit
163 424 ps
160 318 ps
162 412 ps
169 350 ps
163 376 ps
176 354 ps
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
65 117 ps
45 77 ps
68 129 ps
19 63 ps
5 37 ps
51 114 ps
1 The SYSREF± pulse must be at least four DAC clock edges wide plus the setup and hold times in Table 6. For more information, see the Sync Processing Modes
Overview section.
tSYSS
tSYSH
SYSREF+
CLK+
MIN 4 DAC CLOCK EDGES
Figure 2. SYSREF± to DAC Clock Timing Diagram (Only SYSREF+ and CLK+ Shown)
Rev. 0 | Page 7 of 134







AD9164 equivalent, schematic
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
STATIC LINEARITY
IOUTFS = 40 mA, nominal supplies, TA = 25°C, unless otherwise noted.
15
10
5
0
–5
–10
0
10000
20000
30000 40000
CODE
50000
Figure 6. INL, IOUTFS = 20 mA
60000
15
10
5
0
–5
–10
0
10000
20000
30000 40000
CODE
50000
Figure 7. INL, IOUTFS = 30 mA
60000
15
10
5
0
–5
–10
0
10000
20000
30000 40000
CODE
50000
Figure 8. INL, IOUTFS = 40 mA
60000
AD9164
4
2
0
–2
–4
–6
–8
–10
–12
0
10000
20000
30000 40000
CODE
50000
Figure 9. DNL, IOUTFS = 20 mA
60000
4
2
0
–2
–4
–6
–8
–10
–12
0
10000
20000
30000 40000
CODE
50000
Figure 10. DNL, IOUTFS = 30 mA
60000
4
2
0
–2
–4
–6
–8
–10
–12
0
10000
20000
30000 40000
CODE
50000
Figure 11. DNL, IOUTFS = 40 mA
60000
Rev. 0 | Page 15 of 134










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