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PDF ( 数据手册 , 数据表 ) AD7091R-4

零件编号 AD7091R-4
描述 12-Bit SAR ADC
制造商 Analog Devices
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AD7091R-4 数据手册, 描述, 功能
Data Sheet
2-/4-/8-Channel, 1 MSPS,
Ultralow Power, 12-Bit SAR ADC
AD7091R-2/AD7091R-4/AD7091R-8
FEATURES
Ultralow system power
Flexible power/throughput rate management
Normal mode
1.4 mW at 1 MSPS
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
Programmable ALERT interrupt pin (4-/8-channel models)
High performance
1 MSPS throughput with no latency/pipeline delay
SNR: 70 dB typical at 10 kHz input frequency
THD: −80 dB typical at 10 kHz input frequency
INL: ±0.7 LSB typical, ±1.0 LSB maximum
Small system footprint
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
MUXOUT/ADCIN to allow single buffer amplifier
Daisy-chain mode
16-lead, 20-lead, and 24-lead 4 mm × 4 mm LFCSP packages
16-lead, 20-lead, and 24-lead TSSOP packages
Easy to use
SPI/QSPI™/MICROWIRE™/DSP compatible digital interface
Integrated programmable channel sequencer
BUSY indication available (4-/8-channel models)
Built in features for control and monitoring applications
GPOx pins available (4-/8-channel models)
Wide operating range
Temperature range: −40°C to +125°C
Specified for VDD of 2.7 V to 5.25 V
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT ADCIN VDD
REFIN/
REFOUT
REGCAP
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
I/P
MUX
CHANNEL
SEQUENCER
2.5V
VREF
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
ON-CHIP
OSC
CONTROL LOGIC
AND REGISTERS
AD7091R-8
VDRIVE
RESET
CONVST
SDO
SDI
SCLK
CS
GND
Figure 1.
ALERT/
BUSY/
GPO0
GPO1
GND
GENERAL DESCRIPTION
The AD7091R-2/AD7091R-4/AD7091R-8 family is a multichannel
12-bit, ultralow power, successive approximation analog-to-
digital converter (ADC) that is available in two, four, or eight
analog input channel options. The AD7091R-2/AD7091R-4/
AD7091R-8 operate from a single 2.7 V to 5.25 V power supply
and are capable of achieving a sampling rate of 1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 family offers up to eight
single-ended analog input channels with a channel sequencer
that allows a preprogrammed selection of channels to be converted
sequentially. The AD7091R-2/AD7091R-4/ AD7091R-8 also
feature an on-chip conversion clock, an on-chip accurate 2.5 V
reference, and a high speed serial interface.
The AD7091R-2/AD7091R-4/AD7091R-8 have a serial port
interface (SPI) that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The conversion process
and data acquisition are controlled using the CONVST pin.
The AD7091R-2/AD7091R-4/AD7091R-8 use advanced design
techniques to achieve ultralow power dissipation at high
throughput rates. They also feature flexible power management
options. An on-chip configuration register allows the user to set up
different operating conditions. These include power management,
alert functionality, busy indication, channel sequencing, and
general-purpose output pins. The MUXOUT and ADCIN pins
allow signal conditioning of the multiplexer output prior to
acquisition by the ADC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD7091R-4 pdf, 数据表
AD7091R-2/AD7091R-4/AD7091R-8
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
CS 1
RESET 2
16 VDRIVE
15 CONVST
VDD 3
14 SCLK
REGCAP 4 AD7091R-2 13 SDO
REFIN/REFOUT 5
TOP VIEW
(Not to Scale) 12 SDI
GND 6
11 GND
MUXOUT 7
VIN0 8
10 ADCIN
9 VIN1
Figure 5. 2-Channel, 16-Lead TSSOP Pin Configuration
VDD 1
REGCAP 2
REFIN/REFOUT 3
GND 4
AD7091R-2
TOP VIEW
(Not to Scale)
12 SCLK
11 SDO
10 SDI
9 GND
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
Figure 6. 2-Channel, 16-Lead LFCSP Pin Configuration
Table 5. 2-Channel, 16-Lead LFCSP and 16-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP Mnemonic Description
1
15 CS
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on the SPI.
2
16 RESET
Reset. Logic input.
3
1 VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
4
2
REGCAP
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
5
6, 11
3 REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an externally
applied reference is 1.0 V to VDD.
4, 9 GND
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-2.
7
5
MUXOUT
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
8
6 VIN0
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9
7 VIN1
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
10
8 ADCIN
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network
to the MUXOUT pin.
12 10 SDI Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSBs first.
13
11 SDO
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The
bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are required to access the
data. The data is provided MSB first.
14
12 SCLK
Serial Clock. This pin acts as the serial clock input.
15 13 CONVST Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-
and-hold mode into hold mode and initiates a conversion.
16 14 VDRIVE
Not 17
applicable
EPAD
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended values are 10 μF
and 0.1 μF. The voltage range on this pin is 1.8 V to 5.25 V and may be different to the voltage range
at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 8 of 42







AD7091R-4 equivalent, schematic
AD7091R-2/AD7091R-4/AD7091R-8
12
VDRIVE = 1.8V, +125°C VDRIVE = 1.8V, +25°C
10
8
VDRIVE = 3V, +125°C
6
VDRIVE = 1.8V, –40°C
4
VDRIVE = 3V, –40°C
2
VDRIVE = 3V, +25°C
0
10 20 30 40 50
SDO CAPACITANCE LOAD (pF)
Figure 29. tDSDO Delay vs. SDO Capacitance Load and Supply
1.5
CH 0
CH 1
1.0 CH 2
CH 3
CH 4
0.5
CH 5
CH 6
CH 7
0
–0.5
–1.0
–1.5
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 30. Offset Error vs. Temperature
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 31. Offset Error Match vs. Temperature
Data Sheet
100
95
90
85
TA = 25°C
80 fSAMPLE = 1MSPS
VREF = 2.5V EXTERNAL
75
VDD = VDRIVE = 5.00V
VDD = VDRIVE = 3.00V
70
1
10 100
RIPPLE FREQUENCY (kHz)
Figure 32. PSRR vs. Ripple Frequency
1000
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–55
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 33. Gain Error vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–55 –35 –15
5 25 45 65
TEMPERATURE (°C)
85 105 125
Figure 34. Gain Error Match vs. Temperature
Rev. C | Page 16 of 42










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