DataSheet8.cn


PDF ( 数据手册 , 数据表 ) AD9276

零件编号 AD9276
描述 Octal LNA/VGA/AAF/12-Bit ADC and CW I/Q Demodulator
制造商 Analog Devices
LOGO Analog Devices LOGO 


1 Page

No Preview Available !

AD9276 数据手册, 描述, 功能
Octal LNA/VGA/AAF/12-Bit ADC
and CW I/Q Demodulator
AD9276
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz typical at 5 MHz
(gain = 21.3 dB)
SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB
Single-ended input: VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output: 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range: −42 dB to 0 dB
Postamp gain: 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR: 70 dB
SFDR: 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel >160 dBFS/√Hz
Low power: 195 mW per channel at 12 bits/40 MSPS (TGC),
94 mW per channel for CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode: <2 μs
100-lead TQFP_EP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
PRODUCT HIGHLIGHTS
1. Small Footprint.
Eight channels are contained in a small, space-saving
package. Full TGC path, ADC, and I/Q demodulator
contained within a 100-lead, 16 mm × 16 mm TQFP.
2. Low Power.
In TGC mode, low power of 195 mW per channel
at 40 MSPS. In CW mode, ultralow power of 94 mW
per channel.
3. Integrated High Dynamic Range I/Q Demodulator with
Phase Rotation.
4. Ease of Use.
A data clock output (DCO±) operates up to 480 MHz
and supports double data rate (DDR) operation.
5. User Flexibility.
Serial port interface (SPI) control offers a wide range of
flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter.
This filter is placed before the ADC and is programmable
from 8 MHz to 18 MHz.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
12-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.







AD9276 pdf, 数据表
AD9276
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 2.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
CW 4LO INPUTS (4LO+, 4LO−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK, RESET)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
(LOW POWER, REDUCED SIGNAL OPTION)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
LOGIC OUTPUTS (GPO0, GPO1, GPO2, GPO3)
Logic 0 Voltage (IOL = 50 μA)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
250
250
1.2
1.2
1.2
0
247
1.125
Typ Max Unit
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
pF
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
pF
3.6 V
0.3 V
30 kΩ
0.5 pF
3.6 V
0.3 V
70 kΩ
0.5 pF
DRVDD + 0.3 V
0.3 V
30 kΩ
2 pF
1.79 V
0.05 V
LVDS
Offset binary
454
1.375
mV
V
LVDS
Full 150
250 mV
Full 1.10
1.30 V
Offset binary
Full 0.05 V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. 0 | Page 7 of 48







AD9276 equivalent, schematic
500k
450k
400k
350k
300k
250k
200k
150k
100k
50k
0
–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
CODES
Figure 11. Output-Referred Noise Histogram, GAIN+ = 0.0 V
180k
160k
140k
120k
100k
80k
60k
40k
20k
0
–7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7
CODES
Figure 12. Output-Referred Noise Histogram, GAIN+ = 1.6 V
2.0
1.8
1.6
1.4 LNA GAIN = 15.6dB
1.2
LNA GAIN = 17.9dB
1.0
0.8 LNA GAIN = 21.3dB
0.6
0.4
0.2
0
1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 13. Short-Circuit, Input-Referred Noise vs. Frequency,
PGA Gain = 30 dB, GAIN+ = 1.6 V
AD9276
–126
–128
–130
LNA GAIN = 21.3dB
–132
–134
LNA GAIN = 17.9dB
LNA GAIN = 15.6dB
–136
–138
–140
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
GAIN+ (V)
Figure 14. Short-Circuit, Output-Referred Noise vs. GAIN+
64
62 SNR
60
58
SINAD
56
54
52
50
0.4
0.5 0.6 0.7 0.8 0.9 1.0 1.1
GAIN+ (V)
1.2 1.3 1.4
1.5 1.6
Figure 15. SNR/SINAD vs. GAIN+, AIN = −1.0 dBFS
0
–5
–10
MODE I – 40MSPS
–15
MODE III – 80MSPS
MODE II – 65MSPS
–20
–25
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
Figure 16. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = fSAMPLE/3 (Mode I and Mode II), fSAMPLE/4.5 (Mode III)
Rev. 0 | Page 15 of 48










页数 30 页
下载[ AD9276.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
AD9271Octal LAN/VGA/AAF/ADC and Crosspoint SwitchAnalog Devices
Analog Devices
AD9272Octal LNA/VGA/AAF/ADC and Crosspoint SwitchAnalog Devices
Analog Devices
AD9273Octal LNA/VGA/AAF/ADC and Crosspoint SwitchAnalog Devices
Analog Devices
AD9276Octal LNA/VGA/AAF/12-Bit ADC and CW I/Q DemodulatorAnalog Devices
Analog Devices

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap