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PDF ( 数据手册 , 数据表 ) AD9266

零件编号 AD9266
描述 1.8V Analog-to-Digital Converter
制造商 Analog Devices
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AD9266 数据手册, 描述, 功能
Data Sheet
16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9266
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
77.6 dBFS at 9.7 MHz input
71.1 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
56 mW at 20 MSPS
113 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.6/+1.1 LSB
Interleaved data output for reduced pin-count interface
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
SDIO SCLK CSB DRVDD
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
AD9266
SPI
ADC
CORE
PROGRAMMING DATA
OR
D15_D14
8
D1_D0
DCO
REF
SELECT
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
CLK+ CLK–
Figure 1.
PDWN DFS MODE
PRODUCT HIGHLIGHTS
1. The AD9266 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D15_D14 to D1_D0) timing and offset adjustments, and
voltage reference modes.
4. The AD9266 is packaged in a 32-lead RoHS-compliant
LFCSP that is pin compatible with the AD9609 10-bit
ADC, the AD9629 12-bit ADC, and the AD9649 14-bit
ADC, enabling a simple migration path between 10-bit and
16-bit converters sampling from 20 MSPS to 80 MSPS.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD9266 pdf, 数据表
Data Sheet
AD9266
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
AD9266-20/AD9266-40
Temp Min Typ
Max
AD9266-65
AD9266-80
Min Typ Max Min Typ Max Unit
Full
80/320
520
625 MHz
Full 3
20/40 3
65 3
80 MSPS
Full 50/25
15.38
12.5
ns
25.0/12.5
7.69 6.25 ns
Full 1.0
1.0 1.0 ns
Full 0.1
0.1 0.1 ps rms
Full 1.84 3
3.90
Full 1.86 3
4.04
Full −0.53 0.1
0.72
Full 8
Full 350
Full 600/400
Full 2
1.84 3
3.90 1.84 3
3.90 ns
1.86 3
4.04 1.86 3
4.04 ns
−0.53 0.1 0.72 −0.53 0.1 0.72 ns
8 8 Cycles
350 350 μs
300 260 ns
2 2 Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
VIN
CLK+
CLK–
DCO
D1_D0
N–1
D15_D14
tA
N
N+1
tCLK
N+2
N+3
N+5
N+6
N+7
tDCO
tSKEW
D1N–9 D0N–9
D1N–8
tSKEW
D0N–8 D1N–7
D0N–7
D1N–6
D0N–6
D1N–5
D0N–5
D1N–4
D0N–4
tPD
D15N–9 D14N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D15N–5 D14N–5 D15N–4 D14N–4
Figure 2. CMOS Output Data Timing
N+8
Rev. B | Page 7 of 32







AD9266 equivalent, schematic
Data Sheet
AD9266
AD9266-20
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
20MSPS
–20 9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.6dBc
–40
–60
–80
120
SFDRFS
100
SNRFS
80
60 SFDR (dBc)
–100
40
SNR (dBc)
–120
20
–140
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 24. AD9266-20 Single-Tone FFT with fIN = 9.7 MHz
0
–90 –80
–70 –60 –50 –40 –30 –20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 26. AD9266-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
0
20MSPS
–20 30.6MHz @ –1dBFS
SNR = 76.7dB (77.7dBFS)
SFDR = 90.7dBc
–40
–60
–80
–100
–120
–140
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 25. AD9266-20 Single-Tone FFT with fIN = 30.6 MHz
Rev. B | Page 15 of 32










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