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PDF ( 数据手册 , 数据表 ) AD8063

零件编号 AD8063
描述 Rail-to-Rail Amplifiers
制造商 Analog Devices
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AD8063 数据手册, 描述, 功能
Data Sheet
FEATURES
Low cost
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Low offset voltage: 6 mV
High speed
300 MHz, −3 dB bandwidth (G = 1)
650 V/µs slew rate
8.5 nV/√Hz at 5 V
35 ns settling time to 0.1% with 1 V step
Operates on 2.7 V to 8 V supplies
Input voltage range = −0.2 V to +3.2 V with VS = 5 V
Excellent video specifications (RL = 150 Ω, G = 2)
Gain flatness: 0.1 dB to 30 MHz
0.01% differential gain error
0.04° differential phase error
35 ns overload recovery
Low power
6.8 mA/amplifier typical supply current
AD8063 400 µA when disabled
APPLICATIONS
Imaging
Photodiode preamps
Professional video and cameras
Handsets
DVDs/CDs
Base stations
Filters
ADC drivers
Clock buffers
GENERAL DESCRIPTION
The AD8061/AD8062/AD8063 are rail-to-rail output voltage
feedback amplifiers offering ease of use and low cost. They have
a bandwidth and slew rate typically found in current feedback
amplifiers. All have a wide input common-mode voltage range
and output voltage swing, making them easy to use on single
supplies as low as 2.7 V.
Despite being low cost, the AD8061/AD8062/AD8063 provide
excellent overall performance. For video applications, their
differential gain and phase errors are 0.01% and 0.04° into a
Low Cost, 300 MHz
Rail-to-Rail Amplifiers
AD8061/AD8062/AD8063
CONNECTION DIAGRAMS
NC 1
–IN 2
AD8061/
AD8063
8 DISABLE
(AD8063 ONLY)
7 +VS
+IN 3
6 VOUT
–VS
4
(Not to Scale)
5
NC
NC = NO CONNECT
Figure 1. 8-Lead SOIC (R)
VOUT1 1
AD8062
8 +VS
–IN1 2
7 VOUT2
+IN1 3
6 –IN2
–VS 4
(Not to Scale)
5 +IN2
Figure 2. 8-Lead SOIC (R)/MSOP (RM)
AD8063
VOUT 1
6 +VS
VS 2
5 DISABLE
+IN 3
4 IN
(Not to Scale)
Figure 3. 6-Lead SOT-23 (RJ)
AD8061
VOUT 1
5 +VS
–VS 2
+IN 3
4 –IN
(Not to Scale)
Figure 4. 5-Lead SOT-23 (RJ)
3
RF = 50Ω
0
VO = 0.2V p-p
RL = 1kΩ
–3 VBIAS = 1V
RF = 0Ω
–6
IN
–9
RF
50Ω
VBIAS
OUT
RL
–12
1
10 100
FREQUENCY (MHz)
Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω
1k
150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi-
tionally, they offer wide bandwidth to 300 MHz along with
650 V/µs slew rate.
The AD8061/AD8062/AD8063 offer a typical low power of
6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 µA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
Rev. J
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD8063 pdf, 数据表
AD8061/AD8062/AD8063
3
VS = 5V
VO = 1V p-p
RL = 1kΩ
0 VBIAS = 1V
G = –1
–3
G = –2
–6
G = –5
–9
–12
1
10 100
FREQUENCY (MHz)
Figure 13. Large Signal Frequency Response
1k
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
1
VS = 2.7V
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
G = +1
VS = 5V
VS = 3V
10 100
FREQUENCY (MHz)
Figure 14. 0.1 dB Flatness
1k
80
60
40
20
0
– 20
– 40
0.01
GAIN
0.1 1
10
FREQUENCY (MHz)
PHASE
100
200
150
100
50
0
–50
–100
–150
–200
–250
–300
1k
Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency,
VS = 5 V, RL = 1 kΩ
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.5
VS = 5V
RL = 1kΩ
G = +1
2ND @ 1MHz
3RD @ 10MHz
2ND @ 10MHz 3RD @ 1MHz
1.0 1.5 2.0 2.5 3.0
INPUT SIGNAL DC BIAS (V)
3.5
Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
–40 604Ω
5V
10µF
+
–50
0.1µF
1kΩ
–60 52.3Ω
50Ω
1MΩ INPUT
–70
0.1µF +
1.25Vdc
1kΩ
(RLOAD)
–80 2ND H
–90
–100
–110
0.01
3RD H
0.1 1 10
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
50
Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias
–30
VS = 5V
–40 RL = 1kΩ
G = +5
–50
2ND
3RD
VO = 1V p-p
10MHz
–60
–70
–80
–90
–100
–110
–120
0
2ND
3RD 5MHz
1MHz
2ND 3RD
1234
OUTPUT SIGNAL DC BIAS (V)
5
Figure 18. Harmonic Distortion vs. Output Signal DC Bias
Rev. J | Page 8 of 20







AD8063 equivalent, schematic
AD8061/AD8062/AD8063
CAPACITIVE LOAD DRIVE
The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:
Use a small resistor in series with the amplifier’s output and the
load capacitance.
Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
AD8061
RSERIES
VO
VIN CLOAD
Figure 50. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop. Figure 51 plots the capacitance that
produces 30% overshoot vs. noise gain for a typical amplifier.
10k
RS = 4.7
1k
RS = 0
100
10
1 2 34
CLOSED-LOOP GAIN
Figure 51. Capacitive Load vs. Closed-Loop Gain
5
Data Sheet
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown
in Figure 52. When the DISABLE node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 µA, and the AD8063 output
enters a high impedance state. If the DISABLE node is not
connected and allowed to float, the AD8063 stays biased at
full power.
VCC
DISABLE
2V
TO AMPLIFIER
BIAS
VEE
Figure 52. Disable Circuit of the AD8063
Figure 34 shows the AD8063 supply current vs. DISABLE
voltage. Figure 35 plots the output seen when the AD8063 input
is driven with a 10 MHz sine wave, and DISABLE is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
Rev. J | Page 16 of 20










页数 20 页
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