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PDF ( 数据手册 , 数据表 ) AD8037

零件编号 AD8037
描述 Wide Bandwidth Voltage Feedback Clamp Amps
制造商 Analog Devices
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AD8037 数据手册, 描述, 功能
a
Low Distortion, Wide Bandwidth
Voltage Feedback Clamp Amps
AD8036/AD8037
FEATURES
Superb Clamping Characteristics
3 mV Clamp Error
1.5 ns Overdrive Recovery
Minimized Nonlinear Clamping Region
240 MHz Clamp Input Bandwidth
؎3.9 V Clamp Input Range
Wide Bandwidth
AD8036 AD8037
Small Signal
240 MHz 270 MHz
Large Signal (4 V p-p) 195 MHz 190 MHz
Good DC Characteristics
2 mV Offset
10 V/؇C Drift
Ultralow Distortion, Low Noise
–72 dBc typ @ 20 MHz
4.5 nV/Hz Input Voltage Noise
High Speed
Slew Rate 1500 V/s
Settling 10 ns to 0.1%, 16 ns to 0.01%
؎3 V to ؎5 V Supply Operation
APPLICATIONS
ADC Buffer
IF/RF Signal Processing
High Quality Imaging
Broadcast Video Systems
Video Amplifier
Full Wave Rectifier
PRODUCT DESCRIPTION
The AD8036 and AD8037 are wide bandwidth, low distortion
clamping amplifiers. The AD8036 is unity gain stable. The
AD8037 is stable at a gain of two or greater. These devices
allow the designer to specify a high (VCH) and low (VCL) output
clamp voltage. The output signal will clamp at these specified
levels. Utilizing a unique patent pending CLAMPIN™ input
clamp architecture, the AD8036 and AD8037 offer a 10×
improvement in clamp performance compared to traditional
output clamping devices. In particular, clamp error is typically
3 mV or less and distortion in the clamp region is minimized.
This product can be used as a classical op amp or a clamp
amplifier where a high and low output voltage are specified.
The AD8036 and AD8037, which utilize a voltage feedback
architecture, meet the requirements of many applications which
previously depended on current feedback amplifiers. The AD8036
and AD8037 exhibit an exceptionally fast and accurate pulse
response (16 ns to 0.01%), extremely wide small-signal and
CLAMPIN is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
8-Lead Plastic DIP (N), Cerdip (Q),
and SO Packages
NC 1
INPUT 2
+INPUT 3
AD8036/ 8 VH
AD8037
7 +VS
6 OUTPUT
VS 4
(Top View)
5 VL
NC = NO CONNECT
large-signal bandwidths and ultralow distortion. The AD8036
achieves –66 dBc at 20 MHz, and 240 MHz small-signal and
195 MHz large-signal bandwidths. The AD8036 and AD8037’s
recover from 2× clamp overdrive within 1.5 ns. These character-
istics position the AD8036/AD8037 ideally for driving as well as
buffering flash and high resolution ADCs.
In addition to traditional output clamp amplifier applications,
the input clamp architecture supports the clamp levels as addi-
tional inputs to the amplifier. As such, in addition to static dc
clamp levels, signals with speeds up to 240 MHz can be applied
to the clamp pins. The clamp values can also be set to any value
within the output voltage range provided that VH is greater that
VL. Due to these clamp characteristics, the AD8036 and AD8037
can be used in nontraditional applications such as a full-wave
rectifier, a pulse generator, or an amplitude modulator. These
novel applications are only examples of some of the diverse
applications which can be designed with input clamps.
The AD8036 is offered in chips, industrial (–40°C to +85°C)
and military (–55°C to +125°C) package temperature ranges
and the AD8037 in industrial. Industrial versions are available
in plastic DIP and SOIC; MIL versions are packaged in cerdip.
4
AD8036
3
VH = 3V
2 VH = 2V
VH = 1V
1
0
VL = –1V
–1
VL = –2V
–2
VL = –3V
–3
–4
–4 –3 –2 –1 0 1
234
INPUT VOLTAGE – Volts
Figure 1. Clamp DC Accuracy vs. Input Voltage
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







AD8037 pdf, 数据表
AD8036/AD8037
AD8037Typical Characteristics
8
7
6
5
4
3
2
1
0
1
2
1M
VO = 300mV p-p
VS = ؎5V
RL = 100
475
374
274
174
10M
100M
FREQUENCY Hz
1G
TPC 25. AD8037 Small Signal Frequency Response,
G = +2
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1M
VO = 3.00mV p-p
VS = ؎5V
RL = 100
249
224
301
274
10M 100M
FREQUENCY Hz
1G
TPC 26. AD8037 0.1 dB Flatness, N Package
(for R Package Add 20 to RF)
65
60
55
50
45
40
35
30
25
20
15
10
5
0
5
10
15
10k
GAIN
100k
1M 10M
FREQUENCY Hz
PHASE
100
50
0
50
100
150
200
100M
250
1G
TPC 27. AD8037 Open-Loop Gain and Phase Margin
vs. Frequency, RL = 100
350 VS = ؎5V
RL = 100
GAIN = +2
300
RIN RF
100AD8037
49.9
RL
250
R PACKAGE N PACKAGE
200
150
100 150 200 250 300 350 400 450 500 550
VALUE OF RF,RIN
TPC 28. AD8037 Small Signal –3 dB Bandwidth vs. RF, RIN
8
7 RF = 475
6
5 VO = 3.5 V p-p
VS = ؎5V
4 RL = 100
3
2
1
RF = 75
RF = 75
TO
475
BY
100
0
1
2
1M
10M 100M
FREQUENCY Hz
1G
TPC 29. AD8037 Large Signal Frequency Response, G = +2
8
7
6
5
4
3
2
1
0
1
2
100k
VS = ؎5V
VO = 300mV p-p
RL = 100
274
274
AD8037
(VO)
100
1V
VH
VL (VIN)
1M
10M
100M
FREQUENCY Hz
1G
TPC 30. AD8037 Clamp Input Bandwidth, VH, VL
–8– REV. B







AD8037 equivalent, schematic
AD8036/AD8037
40
30
20
10
0
5
10 15
20 25
CLpF
Figure 5. Recommended RSERIES vs. Capacitive Load
INPUT CLAMPING AMPLIFIER OPERATION
The key to the AD8036 and AD8037s fast, accurate clamp and
amplifier performance is their unique patent pending CLAMPIN
input clamp architecture. This new design reduces clamp errors
by more than 10× over previous output clamp based circuits, as
well as substantially increasing the bandwidth, precision and
versatility of the clamp inputs.
Figure 6 is an idealized block diagram of the AD8036 connected
as a unity gain voltage follower. The primary signal path com-
prises A1 (a 1200 V/µs, 240 MHz high voltage gain, differential
to single-ended amplifier) and A2 (a G = +1 high current gain
output buffer). The AD8037 differs from the AD8036 only in
that A1 is optimized for closed-loop gains of two or greater.
The CLAMPIN section is comprised of comparators CH and
CL, which drive switch S1 through a decoder. The unity-gain
buffers in series with +VIN, VH, and VL inputs isolate the input
pins from the comparators and S1 without reducing bandwidth
or precision.
The two comparators have about the same bandwidth as A1
(240 MHz), so they can keep up with signals within the useful
bandwidth of the AD8036. To illustrate the operation of the
CLAMPIN circuit, consider the case where VH is referenced to
1 V, VL is open, and the AD8036 is set for a gain of +1, by con-
necting its output back to its inverting input through the recom-
mended 140 feedback resistor. Note that the main signal path
always operates closed loop, since the CLAMPIN circuit only
affects A1s noninverting input.
If a 0 V to 2 V voltage ramp is applied to the AD8036s +VIN
for the connection just described, VOUT should track +VIN
perfectly up to 1 V, then should limit at exactly 1 V as +VIN
continues to 2 V.
In practice, the AD8036 comes close to this ideal behavior. As
the +VIN input voltage ramps from zero to 1 V, the output of the
high limit comparator CH starts in the off state, as does the out-
put of CL. When +VIN just exceeds VIN (ideally, by say 1 µV,
practically by about 18 mV), CH changes state, switching S1
from Ato Breference level. Since the + input of A1 is now
connected to VH, further increases in +VIN have no effect on the
AD8036s output voltage. In short, the AD8036 is now operat-
ing as a unity-gain buffer for the VH input, as any variation in
VH, for VH > 1 V, will be faithfully reproduced at VOUT.
Operation of the AD8036 for negative input voltages and nega-
tive clamp levels on VL is similar, with comparator CL control-
ling S1. Since the comparators see the voltage on the +VIN pin
as their common reference level, then the voltage VH and VL are
defined as Highor Lowwith respect to +VIN. For example,
if VIN is set to zero volts, VH is open, and VL is +1 V, compara-
tor CL will switch S1 to C,so the AD8036 will buffer the
voltage on VL and ignore +VIN.
The performance of the AD8036 and AD8037 closely matches
the ideal just described. The comparators threshold extends
from 60 mV inside the clamp window defined by the voltages on
VL and VH to 60 mV beyond the windows edge. Switch S1 is
implemented with current steering, so that A1s +input makes a
continuous transition from say, VIN to VH as the input voltage
traverses the comparators input threshold from 0.9 V to 1.0 V
for VH = 1.0 V.
The practical effect of these nonidealities is to soften the transition
from amplification to clamping modes, without compromising
the absolute clamp limit set by the CLAMPIN circuit. Figure 7
is a graph of VOUT vs. VIN for the AD8036 and a typical output
clamp amplifier. Both amplifiers are set for G = +1 and VH = 1 V.
The worst case error between VOUT (ideally clamped) and VOUT
(actual) is typically 18 mV times the amplifier closed-loop gain.
This occurs when VIN equals VH (or VL). As VIN goes above
and/or below this limit, VOUT will settle to within 5 mV of the
ideal value.
In contrast, the output clamp amplifiers transfer curve typically
will show some compression starting at an input of 0.8 V, and
can have an output voltage as far as 200 mV over the clamp limit.
In addition, since the output clamp in effect causes the am-
plifier to operate open loop in clamp mode, the amplifiers out-
put impedance will increase, potentially causing additional errors.
The AD8036s and AD8037s CLAMPIN input clamp architec-
ture works only for noninverting or follower applications and,
since it operates on the input, the clamp voltage levels VH and
VL, and input error limits will be multiplied by the amplifiers
RF
140
VIN
+VIN
VH
VL
+1
+1
+1
A
S1
B
A1
A2
+1
C
CH
CL
S1
VIN > VH
ABC
010
VL VIN VH 1 0 0
VIN < VL
001
VOUT
Figure 6. AD8036/AD8037 Clamp Amp System
–16–
REV. B










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