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PDF ( 数据手册 , 数据表 ) AD8016

零件编号 AD8016
描述 High Output Current xDSL Line Driver
制造商 Analog Devices
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AD8016 数据手册, 描述, 功能
Data Sheet
FEATURES
xDSL line driver that features full ADSL central office (CO)
Performance on ±12 V supplies
Low power operation
±5 V to ±12 V voltage supply
12.5 mA/amp (typical) total supply current
Power reduced keep alive current of 4.5 mA/amp
High output voltage and current drive
IOUT = 600 mA
40 V p-p differential output voltage RL = 50 Ω, VS = ±12 V
Low single-tone distortion
–75 dBc @ 1 MHz SFDR, RL = 100 Ω, VOUT = 2 V p-p
MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 Ω,
PLINE = 20.4 dBm
High Speed
78 MHz bandwidth (–3 dB), G = +5
40 MHz gain flatness
1000 V/μs slew rate
GENERAL DESCRIPTION
The AD8016 high output current dual amplifier is designed for
the line drive interface in Digital Subscriber Line systems such
as ADSL, HDSL2, and proprietary xDSL systems. The drivers
are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
The AD8016 is available in a low cost 24-lead SOIC_W_BAT
and a 28-lead TSSOP_EP with an exposed lead frame (ePAD).
Operating from ±12 V supplies, the AD8016 requires only 1.5 W
of total power dissipation (refer to the Power Dissipation section
for details) while driving 20.4 dBm of power downstream using
Low Power, High Output
Current xDSL Line Driver
AD8016
PIN CONFIGURATIONS
+V1 1
24 +V2
VOUT1
VINN1
VINP1
AGND
2
3
4
5
AGND 6
AGND 7
AGND 8
23 VOUT2
–+ +–
22 VINN2
21 VINP2
20 AGND
AD8016 19 AGND
TOP VIEW
(Not to Scale) 18 AGND
17 AGND
PWDN0 9
16 PWDN1
DGND 10
15 BIAS
–V1 11
14 –V2
NC 12
13 NC
NC = NO CONNECT
Figure 1. 24-Lead SOIC_W_BAT (RB-24)
NC 1
NC 2
NC 3
+VIN2
–VIN2
VOUT2
+V2
4
5
6
7
+V1 8
VOUT1 9
–VIN1 10
+VIN1 11
NC 12
NC 13
NC 14
AD8016ARE
TOP VIEW
(Not to Scale)
28 NC
27 NC
26 NC
25 NC
24 PWDN1
23 BIAS
22 –V2
21 –V1
20 DGND
19 NC
18 PWDN0
17 NC
16 NC
15 NC
NOTES
1. THE EXPOSED PADDLE IS FLOATING,
NOT ELECTRICALLY CONNECTED
INTERNALLY.
2. NC = NO CONNECT.
Figure 2. 28-Lead TSSOP_EP (RE-28-1)
the xDSL hybrid in Figure 35 and Figure 36. Two digital bits
(PWDN0, PWDN1) allow the driver to be capable of full
performance, an output keep-alive state, or two intermediate
bias states. The keep-alive state biases the output transistors
enough to provide a low impedance at the amplifier outputs
for back termination.
The low power dissipation, high output current, high output
voltage swing, flexible power-down, and robust thermal
packaging enable the AD8016 to be used as the central office
(CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary
xDSL systems.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.







AD8016 pdf, 数据表
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–75dBc
VOUT = 100mV
VIN = 20mV
AD8016
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
Figure 6. Multitone Power Ratio; VS = ±12 V, 20.4 dBm Output Power into
100 Ω, Downstream
VOUT = 100mV
TIME (100ns/DIV)
Figure 9. 100 mV Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended
VOUT = 4V
VIN = 20mV
VIN = 800mV
TIME (100ns/DIV)
Figure 7. 100 mV Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended
VOUT = 5V
VIN = 800mV
TIME (100ns/DIV)
Figure 8. 4 V Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended
TIME (100ns/DIV)
Figure 10. 4 V Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended
–30
RF = 499
G = +10
–40 VOUT = 4V p-p
(0,0)
–50 (0,1)
(1,0)
–60
–70
–80
PWDN1, PWDN0 = (1,1)
–90
–100
–110
0.01
0.1 1
FREQUENCY (MHz)
10 20
Figure 11. Distortion vs. Frequency; Second Harmonic, VS = ±12 V, RL = 50 Ω,
Differential
Rev. C | Page 7 of 20







AD8016 equivalent, schematic
Data Sheet
The bias level can be controlled with TTL logic levels (high = 1)
applied to the PWDN1 and PWDN0 pins alone or in combina-
tion with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where ±12 V or ±6 V
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and, thus, quiescent current IQ. By
pulling out a current of 0 μA (or open) to approximately200 μA,
the quiescent current can be adjusted from 100% (full on) to a
full off condition. The full off condition yields a high output
impedance. Because of an on-chip resistor variation of up to
±20%, the actual amount of current required to fully shut down
the AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250 μA is recommended. See Figure 43 for the
logic drive circuit for complete amplifier shutdown. Figure 37
and Figure 38 show the relationship between current pulled out
of the BIAS pin (IBIAS) and the supply current (IQ). A typical
shutdown IQ is less than 1 mA total. Alternatively, an external
pull-down resistor to ground or a current sink attached to the
BIAS pin can be used to set IQ to lower levels (see Figure 44).
The BIAS pin may be used in combination with the PWDN1
and PWDN0 pins; however, diminished MTPR performance
may result when IQ is lowered too much. Current pulled away
from the BIAS pin shunts away a portion of the internal bias
current. Setting PWDN1 or PWDN0 to Logic 0 also shunts
away a portion of the internal bias current. The reduction of
quiescent bias levels due to the use of PWDN1 and PWDN0 is
consistent with the percentages established in Table 7. When
PWDN0 alone is set to Logic 0, and no other means of reducing
the internal bias currents is used, full-rate ADSL signals may be
driven while maintaining reasonable levels of MTPR.
3.3V LOGIC
R2
50k
R1*
2N3904
BIAS
*R1
R1
=
=
47k
22k
FOR
FOR
±±61V2VS.S
OR
+12VS,
Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown
AD8016
THERMAL SHUTDOWN
The AD8016 ARB is designed to incorporate shutdown
protection against accidental thermal overload. In the event
of thermal overload, the AD8016 was designed to shut down
at a junction temperature of 165°C and return to normal
operation at a junction temperature 140°C. The AD8016
continues to operate, cycling on and off, as long as the thermal
overload condition remains. The frequency of the protection
cycle depends on the ambient environment, severity of the
thermal overload condition, the power being dissipated, and
the thermal mass of the PCB beneath the AD8016. When the
AD8016 begins to cycle due to thermal stress, the internal
shutdown circuitry draws current out of the node connected
in common with the BIAS pin, while the voltage at the BIAS
pin goes to the negative rail. When the junction temperature
returns to 140°C, current is no longer drawn from this node,
and the BIAS pin voltage returns to the positive rail. Under
these circumstances, the BIAS pin can be used to trip an alarm
indicating the presence of a thermal overload condition.
Figure 44 also shows three circuits for converting this signal to
a standard logic level.
BIAS
VCC AD8016
200µA
10k
V = VCC – 0.2V
SHUT-
DOWN
BIAS
OR 0µA – 200µA
BIAS
PWDN0 PWDN1
VEE
5V
VCC 10k
10k
5V
1M
ALARM OR BIAS
100k
ALARM
MIN β 350
1/4 HCF 40109B
SGS–THOMSON
Figure 44. Shutdown and Alarm Circuit
Rev. C | Page 15 of 20










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