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PDF ( 数据手册 , 数据表 ) LC72131KMA

零件编号 LC72131KMA
描述 PLL Frequency Synthesizer
制造商 ON Semiconductor
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LC72131KMA 数据手册, 描述, 功能
Ordering number : ENA0788A
LC72131K
LC72131KMA
CMOS IC
PLL Frequency Synthesizer
Overview
The LC72131K and LC72131KMA are PLL frequency synthesizers for use in tuners in radio/cassette players.
They allow high-performance AM/FM tuners to be implemented easily.
Features
High speed programmable dividers
FMIN: 10 to 160MHz …………………….. pulse swallower (built-in divide-by-two prescaler)
AMIN: 2 to 40MHz ………………………. pulse swallower
0.5 to 10MHz …………………….. direct division
IF counter
IFIN: 0.4 to 12MHz ………………………. AM/FM IF counter
Reference frequencies
Twelve selectable frequencies (4.5 or 7.2MHz crystal)
100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1kHz
Phase comparator
Dead zone control
Unlock detection circuit
Deadlock clear circuit
Built-in MOS transistor for forming an active low-pass filter
I/O ports
Dedicated output ports: 4 Input or output ports: 2 Support clock time base output
Serial data I/O
Support CCB format communication with the system controller.
Continued on next page.
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
June, 2013
O3112HK 20120919-S00009/51407HKIM 20070328-S00008,S00009 No.A0788-1/22







LC72131KMA pdf, 数据表
LC72131K, LC72131KMA
Continued from preceding page.
Symbol
Pin No.
LC72131K LC72131KMA
PD 18
16
Type
Charge pump
output
AIN
AOUT
19
20
17 LPF amplifier
18 transistors
Functions
PLL charge pump output
When the frequency generated by dividing the local oscillator
frequency by N is higher than the reference frequency, a high
level is output from the PD pin.
Similarly, when that frequency is lower, a low level is output.
The PD pin goes to the high impedance state when the
frequencies match.
The n-channel MOS transistor used for the PLL active
low-pass filter.
Circuit configuration
IFIN 12
11 IF counter
Accepts an input in the frequency range 0.4 to 12MHz.
The input signal is directly transmitted to the IF counter.
The result is output starting the MSB of the IF counter using the
DO pin.
Four measurement periods are supported: 4, 8, 32, and 64ms.
DI Control Data (Serial Data Input) Structure
[1] IN1 mode
address
DI 0 0 0 1 0 1 0 0
First Data IN1
[2] IN2 mode
address
DI 1 0 0 1 0 1 0 0
First Data IN2
No.A0788-8/22







LC72131KMA equivalent, schematic
IF Counter Operation
CE
Frequncy
Measurement
time
IFIN
LC72131K, LC72131KMA
CTE data=1
Wait time
Measurement
time
GT
Count start
Count end (end-UC)
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.
The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the
LC72131K/KMA when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the
period between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF
counter at the end of the measurement period must be read out during the period that CTE is 1. This is because the IF
counter is reset when CTE is set to 0.
Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an
IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is
possible for IF buffer leakage output to cause incorrect stops at points where there is no station.
IFIN minimum input sensitivity standard
f [MHz]
IFS 0.4f<0.5
0.5f<8
8f12
1: Normal mode
40mVrms (0.1 to 3mVrms)
40mVrms
40mVrms (1 to 10mVrms)
0: Degradation mode
70mVrms (10 to 15mVrms)
70mVrms
70mVrms (30 to 40mVrms)
Note: Values in parentheses are actual performance values presented as reference data.
Unlock Detection Timing
Unlock Detection Determination Timing
Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,
unlock determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.
CE
DATA
LATCH
Old data
New data
VCO/N
N-
counter
Old divisor N
New divisor N’
fref
φERROR
(unlock)
The divisor N is not updated
during the first period.
Note: After changing the divisor, φERROR
is output after two fref periods.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1kHz, i.e., the period is 1ms, after changing the divisor N, the system must wait at least 2ms
before checking for the unlocked state.
No.A0788-16/22










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