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PDF ( 数据手册 , 数据表 ) ADV7123

零件编号 ADV7123
描述 Triple 10-Bit High Speed Video DAC
制造商 Analog Devices
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ADV7123 数据手册, 描述, 功能
CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
ADV7123
FEATURES
330 MSPS throughput rate
Triple 10-bit digital-to-analog converters (DACs)
SFDR
−70 dB at fCLK = 50 MHz; fOUT = 1 MHz
−53 dB at fCLK = 140 MHz; fOUT = 40 MHz
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal reference (1.235 V)
Single-supply 5 V/3.3 V operation
48-lead LQFP package
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) package
APPLICATIONS
Digital video systems (1600 × 1200 @ 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
GENERAL DESCRIPTION
The ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 10-bit, video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite SYNC and BLANK.
The ADV7123 also has a power save mode.
FUNCTIONAL BLOCK DIAGRAM
VAA
BLANK
SYNC
BLANK AND
SYNC LOGIC
R9 TO R0 10
DATA
REGISTER
10
DAC
G9 TO G0 10
DATA
REGISTER
10
DAC
B9 TO B0 10
DATA
REGISTER
10
DAC
PSAVE
CLOCK
POWER-DOWN
MODE
VOLTAGE
REFERENCE
CIRCUIT
ADV7123
GND
RSET COMP
Figure 1.
IOR
IOR
IOG
IOG
IOB
IOB
VREF
The ADV7123 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
PRODUCT HIGHLIGHTS
1. 330 MSPS throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
ADV is a registered trademark of Analog Devices, Inc.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.







ADV7123 pdf, 数据表
ADV7123
Parameter
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
TMIN to TMAX
fCLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk3
Data Feedthrough4, 5
Clock Feedthrough4, 5
Min Typ Max Unit
66 dBc
65 dBc
64 dBc
64 dBc
55 dBc
10 pV-sec
23 dB
22 dB
33 dB
1 These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5 TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 5.
Parameter3
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time4
Analog Output Transition Time5
Analog Output Skew6
CLOCK CONTROL
CLOCK Frequency7
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
PSAVE Up Time6
Symbol
t6
t7
t8
t9
fCLK
t1
t2
t3
t4
t5
t4
t5
t4
t5
tPD
t10
Min
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Typ Max
5.5
1.0
15
12
50
140
240
1.0 1.0
2 10
Unit
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
Conditions
50 MHz grade
140 MHz grade
240 MHz grade
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Rev. D | Page 7 of 24







ADV7123 equivalent, schematic
ADV7123
–5 –5
–45 –45
–85
0kHz
START
35MHz
70MHz
STOP
Figure 19. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 2 MHz)
–5
–85
0kHz
START
35MHz
70MHz
STOP
Figure 21. Dual-Tone SFDR @ fCLK = 140 MHz (fOUT1 = 13.5 MHz, fOUT2 = 14.5 MHz)
–45
–85
0kHz
START
35MHz
70MHz
STOP
Figure 20. Single-Tone SFDR @ fCLK = 140 MHz (fOUT = 20 MHz)
Rev. D | Page 15 of 24










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