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PDF ( 数据手册 , 数据表 ) AD9245

零件编号 AD9245
描述 3V A/D Converter
制造商 Analog Devices
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AD9245 数据手册, 描述, 功能
Data Sheet
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converter
AD9245
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9245
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
16
3
REF
SELECT
CORRECTION LOGIC
14
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OTR
D13 (MSB)
D0 (LSB)
AGND
CLK PDWN MODE DGND
Figure 1.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD9245 pdf, 数据表
Data Sheet
AD9245
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted.
Table 5.
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS (D0 to D13, OTR)2
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-801
Min Typ Max
2.0
–10
–10
2
0.8
+10
+10
3.29
3.25
0.2
0.05
2.49
2.45
0.2
0.05
1 AD9245BCP-80 performance measured with 1.0 V external reference.
2 Output voltage levels measured with 5 pF load on each output.
Unit
V
V
µA
µA
pF
V
V
V
V
V
V
V
V
Rev. E | Page 7 of 32







AD9245 equivalent, schematic
Data Sheet
AD9245
75
74
–40C
73 +25C
72
71
+85C
70
69
68
67
66
65
0 25 50 75 100
INPUT FREQUENCY (MHz)
Figure 20. SNR vs. Input Frequency
90
SFDR (DCS ON)
88
86
84
SFDR (DCS OFF)
82
80
78
76
74
72
70
30
SNR (DCS OFF)
SNR (DCS ON)
35 40 45 50 55 60
DUTY CYCLE (%)
Figure 21. SNR/SFDR vs. Clock Duty Cycle
65
125
70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
9.6 19.2
FREQUENCY (MHz)
28.8
38.4
Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS
100
95
90
85 –40C
80 +25C
+85C
75
70
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25 50 75 100
INPUT FREQUENCY (MHz)
Figure 23. SFDR vs. Input Frequency
9.6 19.2
FREQUENCY (MHz)
28.8
Figure 24. Two 32K FFT CDMA-2000 Carriers @
FIN = 46.08 MHz; Sample Rate = 61.44 MSPS
9.6 19.2
FREQUENCY (MHz)
28.8
Figure 25. Two 32K FFT WCDMA Carriers @
FIN = 76.8 MHz; Sample Rate = 61.44 MSPS
125
38.4
38.4
Rev. E | Page 15 of 32










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