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PDF ( 数据手册 , 数据表 ) AD9214

零件编号 AD9214
描述 3V A/D Converter
制造商 Analog Devices
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AD9214 数据手册, 描述, 功能
a
FEATURES
SNR = 57 dB @ 39 MHz Analog Input (–0.5 dBFS)
Low Power
190 mW at 65 MSPS
285 mW at 105 MSPS
30 mW Power-Down Mode
300 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1 V p-p or 2 V p-p Analog Input Range Option
Single 3.3 V Supply Operation (2.7 V–3.6 V)
Two’s Complement or Offset Binary Data Format Option
APPLICATIONS
Battery-Powered Instruments
Hand-Held Scopemeters
Low-Cost Digital Oscilloscopes
Ultrasound Equipment
Cable Reverse Path
Broadband Wireless
Residential Power Line Networks
10-Bit, 65/80/105 MSPS
3 V A/D Converter
AD9214
FUNCTIONAL BLOCK DIAGRAM
AD9214
AIN
BUFFER
AIN
ENCODE
AVDD PWRDWN
DrVDD
PIPELINE 10
T/H ADC
CORE
TIMING
REF
DFS/GAIN
OR
10
D9–D0
AGND REF REFSENSE
DGND
PRODUCT DESCRIPTION
The AD9214 is a 10-bit monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit, and
is optimized for low cost, low power, small size, and ease of use.
The product operates up to 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
The ADC requires only a single 3.3 V (2.7 V to 3.6 V) power
supply and an encode clock for full performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
The clock input is TTL/CMOS compatible. In the power-down
state, the power is reduced to 30 mW. A gain option allows
support for either 1 V p-p or 2 V p-p analog signal input swing.
Fabricated on an advanced CMOS process, the AD9214 is
available in a 28-lead surface-mount plastic package (28-SSOP)
specified over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
High Performance—Outstanding ac performance from 65 MSPS
to 105 MSPS. SNR greater than 55 dB typical and as high
as 58 dB.
Low Power—The AD9214 at 285 mW consumes a fraction of
the power available in existing high-speed monolithic solutions.
In sleep mode, power is reduced to 30 mW.
Single Supply—The AD9214 uses a single 3 V supply, simplify-
ing system power supply design. It also features a separate digital
output driver supply line to accommodate 2.5 V logic families.
Small Package—The AD9214 is packaged in a small 28-lead
surface-mount plastic package (28-SSOP).
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002







AD9214 pdf, 数据表
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differen-
tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak-to-peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
SINADMEASURED
1.76
dB
+
20 log

Full Scale
Actual 
ENOB =
6.02
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic 1state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing tENCH in text. At a
given clock rate, these specs define an acceptable Encode duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
V
2
FULL
SCALE
rms
PowerFULL SCALE = 10 log

ZINPUT
0.001

Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
AD9214
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for any range within the ADC)
VNOISE =
Z × 0.001 × 10 FSdBm SNRdBc SignaldBFS
10
Where Z is the input impedance, FS is the full-scale of the
device for the frequency in question, SNR is the value for the
particular input level and Signal is the signal level within the
ADC reported in dB below full-scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May
be reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
REV. D
–7–







AD9214 equivalent, schematic
AD9214
AD9214/PCB Bill of Material
# Quantity Reference Designator
Device
Package
11
2 19
34
41
54
64
74
81
92
10 37
11 3
12 1
13 1
14 1
15 1
16 1
17 1
18 3
N/A
C1C3, C5C14, C16C20, C25C28
C21C24
C4
R1, R2, R4, R8
R7, R10, R12, R17
U5U8
R21
R6, R9
E1E6, E8E9, E11E27, E29, E31E41
J1, J2, J5
U12
U11
U3
U1
U2
T1
U4, U9, U10
PCB
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Test Points
Jumper Connections
Connector
Clock Chip
DAC
Latch
ADC/DUT
40-Pin Header
Transformer
Power Strip
Power Connector
603
CAPTAJD
603
1206
1206
RPAK_742
1206
1206
SMB
SOIC
SOIC
SOIC
SOIC
The following items are included in the PCB design, but are omitted at assembly.
19 3
20 2
21 1
22 4
23 1
24 1
25 3
26 2
27 3
28 1
29 1
C1, C20, C28
C30, C29
C15
R5, R18, R25, R26
R23
R24
R11, R15, R16
R13, R14
R27, R28, R3
R19
Z1
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Op Amp
603
CAPTAJD
603
1206
1206
1206
1206
1206
1206
1206
SOIC
Value
0.1 µF
10 µF
0.01 µF
25
50
100
0
2000
TSW-120-07-G-S
SMT-100-BK-G
51-52-220
SN74LVC86
AD9752
74LCX821
AD9214
Samtec TSW-120-07-G-D
Mini Circuits ADT1-1WT
Newark 95F5966
25.602.5453.0
0.1 µF
10 µF
15 pF
500
1 k
4 k
User Select
N/A
50
0
AD8138
REV. D
–15–










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