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PDF ( 数据手册 , 数据表 ) ADF4218L

零件编号 ADF4218L
描述 Dual Low Power Frequency Synthesizers
制造商 Analog Devices
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ADF4218L 数据手册, 描述, 功能
a
Dual Low Power
Frequency Synthesizers
ADF4217L/ADF4218L/ADF4219L
FEATURES
Total IDD: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate VP Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
IFINA
IFINB
ADF4217L
ADF4218L
ONLY
REFIN
CLOCK
DATA
LE
RFINA
RFINB
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY
NC VDD1 VDD2
VP1
VP2
N = BP + A
IF
PRESCALER
BUFFER
11(13)-BIT IF
B COUNTER
6(5)-BIT IF
A COUNTER
PHASE
COMPARATOR
ADF4217L/
ADF4218L/
ADF4219L
CHARGE
PUMP
CPIF
IF
LOCK
DETECT
22-BIT
DATA SDOUT
REGISTER
14(15)-BIT IF
R COUNTER
14(15)-BIT RF
R COUNTER
OUTPUT
MUX
MUXOUT
RF
LOCK
DETECT
N = BP + A
RF
PRESCALER
11(13)-BIT RF
B COUNTER
6(5)-BIT RF
A COUNTER
PHASE
COMPARATOR
CHARGE
PUMP
CPRF
REV. C
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
DGNDRF AGNDRF DGNDIF AGNDIF
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.







ADF4218L pdf, 数据表
ADF4217L/ADF4218L/ADF4219L
0
REFERENCE
VDD = 3V, VP = 5V
–10
LEVEL = –4.2dBm
ICP = 4.0mA
PFD FREQUENCY = 200kHz
–20 LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10kHz
–30 VIDEO BANDWIDTH = 10kHz
SWEEP = 1.9 SECONDS
–40 AVERAGES = 20
–50
–60
–70
–80 –83dBc
–90
–100
–400kHz
–200kHz 900MHz 200kHz
FREQUENCY
400kHz
TPC 7. Reference Spurs, IF Side
(900 MHz, 200 kHz, 20 kHz)
10dB/DIVISION
–40
RL = –40dBc/Hz
rms NOISE = 0.9؇
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
TPC 8. Integrated Phase Noise, IF Side
(900 MHz, 200 kHz, 20 kHz)
–120
–130
VDD = 3V
VP = 5V
–140
–150
–160
–170
–180
1
10 100 1000
PHASE DETECTOR FREQUENCY – kHz
10000
TPC 9. Phase Noise Referred to CP Output vs.
PFD Frequency, RF Side
–120
–130
VDD = 3V
VP = 5V
–140
–150
–160
–170
–180
1
10 100 1000
PHASE DETECTOR FREQUENCY – kHz
10000
TPC 10. Phase Noise Referred to CP Output vs.
PFD Frequency, IF Side
–60
VDD = 3V
VP = 5V
–70
–80
–90
–100
–40
–20
0 20 40 60
TEMPERATURE – ؇C
80 100
TPC 11. Phase Noise vs. Temperature, RF Side
(1960 MHz, 200 kHz, 20 kHz)
–60
VDD = 3V
VP = 5V
–70
–80
–90
–100
–40
–20
0 20 40 60
TEMPERATURE – ؇C
80 100
TPC 12. Phase Noise vs. Temperature, IF Side
(900 MHz, 200 kHz, 20 kHz)
–8– REV. C







ADF4218L equivalent, schematic
ADF4217L/ADF4218L/ADF4219L
Table VII. RF Reference Counter Latch Map
RF REFERENCE COUNTER LATCH
14-BIT REFERENCE COUNTER, R
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P12 P11 P10 P13 P9 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (1) C1 (0)
P9 PD POLARITY
0 NEGATIVE
1 POSITIVE
P13 ICP
0 1.0mA
1 4.0mA
CHARGE PUMP
P10 OUTPUT
0 NORMAL
1 THREE-STATE
R15 R14 R13 R12
..........
R3
R2 R1 DIVIDE RATIO
00 0 0
..........
0
0 11
00 0 0
..........
0
1 02
00 0 0
..........
0
1 13
00 0 0
..........
1
0 04
.. . .
..........
.
. ..
.. . .
..........
.
. ..
.. . .
..........
.
. ..
01 1 1
..........
1
0 0 16380
01 1 1
..........
1
0 1 16381
01 1 1
..........
1
1 0 16382
01 1 1
..........
1
1 1 16383
.. . .
..........
.
. ..
11 1 1
..........
1
1 1 32767
P4 P3
P12 P11 FROM RF R LATCH MUXOUT
0 00
0 LOGIC LOW STATE
0 00
1 IF ANALOG LOCK DETECT
0 X1
0 IF REFERENCE DIVIDER OUTPUT
0 X1
1 IF N DIVIDER OUTPUT
0 10
0 RF ANALOG LOCK DETECT
0 10
1 RF/IF ANALOG LOCK DETECT
1 X0
0 RF REFERENCE DIVIDER
1 X0
1 RF N DIVIDER
1 01
0 FAST LOCK OUTPUT SWITCH ON
AND CONNECTED TO MUXOUT
1 01
1 IF COUNTER RESET
1 11
0 RF COUNTER RESET
1 11
1 IF AND RF COUNTER RESET
–16–
REV. C










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