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PDF ( 数据手册 , 数据表 ) ADF4112

零件编号 ADF4112
描述 RF PLL Frequency Synthesizers
制造商 Analog Devices
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ADF4112 数据手册, 描述, 功能
Data Sheet
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width
with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
24-BIT
INPUT REGISTER 22
SDOUT
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
19
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
LOCK
DETECT
CURRENT CURRENT
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM
FUNCTION
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P +1
LOAD
LOAD
6-BIT
A COUNTER
AVDD
SDOUT
MUX
HIGH Z
M3 M2 M1
ADF4110/ADF4111
6 ADF4112/ADF4113
CE
AGND
DGND
Figure 1. Functional Block Diagram
CP
MUXOUT
Rev. F
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
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Technical Support
www.analog.com







ADF4112 pdf, 数据表
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
FREQ
–UNIT
GHz
FREQ
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
PARAM
–TYPE
S
MAGS11
0.89207
0.8886
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
DATA
KEYWORD IMPEDANCE
–FORMAT
–OHMS
MA R
50
ANGS11
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
–13.52
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
–36.961
–39.343
FREQ
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
MAGS11
0.9512
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
ANGS11
–40.134
–43.747
–44.393
–46.937
–49.6
–51.884
–51.21
–53.55
–56.786
–58.781
–60.545
–61.43
–61.241
–64.051
–66.19
–63.775
Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz)
0
–5 VDD = 3V
VP = 3V
–10
–15
TA = +25°C
–20 TA = +85°C
–25
–30
–35
0
TA = –40°C
123
4
RF INPUT FREQUENCY (GHz)
5
0
–10
REFERENCE
LEVEL = –4.2dBm
VDD = 3V, VP = 5V
ICP = 5mA
–20 PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
–30 RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
–40 SWEEP = 1.9 s
AVERAGES = 19
–50
–60
–70 –92.5dBc/Hz
–80
–90
–100
–2.0kHz
–1.0kHz 900MHz
1.0kHz
FREQUENCY
2.0kHz
Figure 8. ADF4113 Phase Noise
(900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled
–40
–50
–60
RMS NOISE = 0.52°
–70 RL = –40dBc/Hz
–80
–90
–100
–110
–120
–130
–140
100
1k 10k 100k
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
1M
Figure 6. Input Sensitivity (ADF4113)
0
–10
REFERENCE
LEVEL = –4.2dBm
VDD = 3V, VP = 5V
ICP = 5mA
–20 PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
–30 RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
–40 SWEEP = 1.9 s
AVERAGES = 19
–50
–60
–70 –91.0dBc/Hz
–80
–90
–100
–2.0kHz
–1.0kHz 900MHz
1.0kHz
FREQUENCY
2.0kHz
Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
Figure 9. ADF4113 Integrated Phase Noise
(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs)
–40
–50
–60
RMS NOISE = 0.62°
–70 RL = –40dBc/Hz
–80
–90
–100
–110
–120
–130
–140
100
1k
10k 100k
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
1M
Figure 10. ADF4113 Integrated Phase Noise
(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs)
Rev. F | Page 8 of 28







ADF4112 equivalent, schematic
ADF4110/ADF4111/ADF4112/ADF4113
Table 8. AB Counter Latch Map
Data Sheet
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)
X = DON'T CARE
A6
A5 ••••••••• •
A2
A1
A COUNTER
DIVIDE RATIO
0
0 ••••••••• • 0
0
0
0
0 ••••••••• • 0
1
1
0
0 ••••••••• • 1
0
2
0
0 ••••••••• • 1
1
3
• ••••••••• • •
• ••••••••• • •
• ••••••••• • •
1
1 ••••••••• • 0
0
60
1
1 ••••••••• • 0
1
61
1
1 ••••••••• • 1
0
62
1
1 ••••••••• • 1
1
63
B13
B12
B11 ••••••••• •
B3
B2
0
0
0 ••••••••• •
0
0
0
0
0 ••••••••• •
0
0
0
0
0 ••••••••• •
0
1
0
0
0 ••••••••• •
0
1
0
0
0 ••••••••• •
1
0
• ••••••••• •
• ••••••••• •
• ••••••••• •
1
1
1 ••••••••• •
1
0
1
1
1 ••••••••• •
1
0
1
1
1 ••••••••• • 1
1
1
1
1 ••••••••• • 1
1
B1 B COUNTER DIVIDE RATIO
0 NOT ALLOWED
1 NOT ALLOWED
0 NOT ALLOWED
13
04
••
••
••
0 8188
1 8189
0 8190
1 8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
0
0
1
1
*SEE TABLE 9
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
CP GAIN
0
1
0
1
OPERATION
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED.
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED.
CHARGE PUMP CURRENT SETTING 1
IS USED.
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH, B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (NX FREF), AT THE OUTPUT, NMIN IS (P2–P).
Rev. F | Page 16 of 28










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