DataSheet8.cn


PDF ( 数据手册 , 数据表 ) HI-3593

零件编号 HI-3593
描述 3.3V ARINC 429 Dual Receiver / Single Transmitter
制造商 HOLTIC
LOGO HOLTIC LOGO 


1 Page

No Preview Available !

HI-3593 数据手册, 描述, 功能
August 2013
HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top View)
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
FEATURES
· ARINC 429 specification compliant
· Single 3.3V power supply
· On-chip analog line driver and receiver connect
directly to ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13







HI-3593 pdf, 数据表
HI-3593
ARINC 429 BIT ORDERING
ARINC 429 messages consist of a 32-bit sequence as shown
below. The first eight bits that appear on the ARINC 429 bus are
the label byte. The next twenty three bits comprise a data field
which presents data in a variety of formats defined in the ARINC
429 specification. The last bit transmitted is an odd parity bit.
ARINC 429 data is transmitted between the HI-3593 and host
microcontroller using the four-wire Serial Peripheral Interface
(SPI). A read or write operation consists of a single-byte op-code
followed by the data. When writing to the transmit FIFO or reading
from the receive FIFOs, the SPI data field is four bytes. Figure 1
shows how the SPI data bytes are mapped to the ARINC 429
message.
ARINC 429 specifies the MSB of the label as ARINC bit 1.
Conversely, the data field MSB is bit 31. So the bit significance of
the label byte and data fields are opposite.
The HI-3593 may be programmed to “flip” the bit ordering of the
label byte as soon as it is received and immediately prior to
transmission. This is accomplished by setting the TFLIP bit to a “1”
in the Transmit Control Register and/or the RFLIP bit in the
Receive Control Registers. The RFLIP bit does not control Priority
Label Match Registers.
Note that when reading ARINC 429 messages from the Priority-
Label Registers the label byte is omitted to permit a faster read
time. The label value will match the value loaded into the Match
Register and therefore does not need to be output each time a
message is read.
ARINC 429 Message as received / transmitted on the ARINC 429 serial bus
MSB LABEL LSB
LSB
DATA
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
time
ARINC 429 Message as transferred on the SPI bus
SPI Op-Code
MSB
DATA
LSB LSB LABEL MSB
0 0 0 0 1 1 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Example 1. Write Transmit FIFO (Op-Code 0x0C) with TFLIP bit = “0”.
SPI Op-Code
MSB
DATA
LSB MSB LABEL LSB
1 0 1 0 0 0 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
Example 2. Read Receiver 1 FIFO (Op-Code 0xA0) with RFLIP bit = “1”.
SPI Op-Code
MSB
DATA
LSB
1 1 0 0 1 1 0 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Example 3. Read Receiver 2 Priority-Label Register #3 (Op-Code 0xCC).
SPI Op-Code
MSB LABEL #3 LSB MSB LABEL #2 LSB MSB LABEL #1 LSB
00 10 1100 12345678 12345678 12345678
Example 4. Write Receiver 2 Priority-Label Match Registers (Op-Code 0x2C)with RFLIP bit = “1” or “0”.
FIGURE 1. ARINC 429 & SPI BIT ORDERING
HOLT INTEGRATED CIRCUITS
8







HI-3593 equivalent, schematic
TIMING DIAGRAMS
HI-3593
CS
SCK
tCHH
SI
t DS
SERIAL INPUT TIMING DIAGRAM
t CYC
t CES
t SCKF
MSB
t DH
t SCKR
t CPH
t CEH
LSB
CS
SCK
SO
SERIAL OUTPUT TIMING DIAGRAM
t SCKH
tSCKL
t CYC
Hi Impedance
t DV
MSB
t CPH
t CHZ
LSB
Hi Impedance
TXAOUT
TXBOUT
DATA RATE - EXAMPLE PATTERN
ARINC BIT
DATA
NULL
BIT 30
DATA
NULL
BIT 31
DATA
NULL
BIT 32
WORD GAP
ARINC DATA
FLAGS (1)
R1INT / R2INT
CS
SI
SO
BIT 31
BIT 32
RECEIVER OPERATION
tRFLG
tINTW
tRXR
tSPIF
SPI INSTRUCTION (E.g. 0xA0)
ARINC
BIT 32
ARINC
BIT 31
ARINC
BIT 30
(1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3
BIT 1
NEXT WORD
ARINC
BIT 1
HOLT INTEGRATED CIRCUITS
16










页数 23 页
下载[ HI-3593.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
HI-35933.3V ARINC 429 Dual Receiver / Single TransmitterHOLTIC
HOLTIC
HI-3596Octal ARINC 429 ReceiversHOLTIC
HOLTIC
HI-3597Octal ARINC 429 ReceiversHOLTIC
HOLTIC
HI-3598Octal ARINC 429 ReceiversHOLTIC
HOLTIC

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap