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PDF ( 数据手册 , 数据表 ) HI-3210

零件编号 HI-3210
描述 Octal Receiver / Quad Transmitter
制造商 HOLTIC
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HI-3210 数据手册, 描述, 功能
August 2013
HI-3210
ARINC 429 DATA MANAGEMENT ENGINE /
Octal Receiver / Quad Transmitter
GENERAL DESCRIPTION
The HI-3210 from Holt Integrated Circuits is a single chip
CMOS data management IC capable of managing, storing
and forwarding avionics data messages between eight
ARINC 429 receive channels and four ARINC 429 transmit
channels.
The ARINC 429 buses may be operated independently,
allowing a host CPU to send and receive data on multiple
buses, or the HI-3210 can be programmed to automati-
cally re-format, re-label, re-packetize and re-transmit data
from ARINC 429 receive buses to ARINC 429 transmit
buses.
A 32K x 8 on-board memory allows received data to be
logically organized and automatically updated as new
ARINC 429 labels are received.
An auto-initialization feature allows configuration informa-
tion to be up-loaded from an external EEPROM on reset to
facilitate rapid start-up or operation without a host CPU.
The HI-3210 interfaces directly with Holt’s HI-8448 octal
ARINC 429 receiver IC and HI-8592 or HI-8596 ARINC
429 line drivers.
FEATURES
· Eight ARINC 429 Receive channels
· Four ARINC 429 Transmit channels
· 32KB on chip user-configurable data storage
memory
· Programmable received data filtering
· Programmable transmission schedulers for periodic
ARINC 429 broadcasting
· SPI Host CPU interface
· Auto-initialization feature allows power-on
configuration or independent operation without CPU
PIN CONFIGURATION
APPLICATION
CPU
Memory
Controller
HI-3210
AACK 1
ARXBIT6 2
AINT 3
ARXBIT7 4
SCANSHIFT 5
ARX2N 6
ARX3P 7
VDD 8
GND 9
ARX3N 10
ARX4P 11
ARX4N 12
ARX5P 13
ARX5N 14
ARX6P 15
ARX6N 16
HI-3210PQI
&
HI-3210PQT
48 ARXBIT3
47 ATXSLP0
46 ATX0N
45 ATX0P
44 ATX1N
43 ATX1P
42 ATXSLP1
41 VDD
40 GND
39 ARXBIT2
38 ATXSLP2
37 ATX2N
36 ATX2P
35 ATX3N
34 ATX3P
33 ATXSLP3
64 - Pin Plastic Quad Flat Pack (PQFP)
(See ordering information for additional pin configurations)
(DS3210 Rev. D)
08/13







HI-3210 pdf, 数据表
HI-3210
HI-3210 REGISTER MAP
ADDRESS R/W
REGISTER
MNEMONIC DESCRIPTION
0x8000
0x8001
0x8002
0x8003
0x8004
0x8005
0x8006
0x8007
0x8008
0x8009
0x800A
0x800B
0x800C
0x800D
0x800E
0x800F
0x8010
0x8011
0x8012
0x8013
0x8014
0x8015
0x8016
0x8017
0x8018
0x8019
0x801A
0x801B
0x801C
0x801D
0x801E
0x801F
0x8020
0x8021
0x8022
0x8029
0x802A
0x802B
0x802C
0x802D
0x802E
0x802F
0x8034
0x8035
R* ARINC 429 Rx PENDING INTERRUPT
R ARINC 429 Rx INTERRUPT ADDRESS 0
R ARINC 429 Rx INTERRUPT ADDRESS 1
R ARINC 429 Rx INTERRUPT ADDRESS 2
R ARINC 429 Rx INTERRUPT ADDRESS 3
R ARINC 429 Rx INTERRUPT ADDRESS 4
R ARINC 429 Rx INTERRUPT ADDRESS 5
R ARINC 429 Rx INTERRUPT ADDRESS 6
R ARINC 429 Rx INTERRUPT ADDRESS 7
- RESERVED
R* PENDING INTERRUPT REGISTER
R RESERVED
R MUXED FIFO FLAGS
R ARINC 429 TX READY BITS
R MASTER STATUS REGISTER
R/W
MASTER CONTROL REGISTER
APIR
AIAR0
AIAR1
AIAR2
AIAR3
AIAR4
AIAR5
AIAR6
AIAR7
PIR
AMFF
ATRB
MSR
MCR
R/W ARINC 429 RX CONTROL REGISTER 0
R/W ARINC 429 RX CONTROL REGISTER 1
R/W ARINC 429 RX CONTROL REGISTER 2
R/W ARINC 429 RX CONTROL REGISTER 3
R/W ARINC 429 RX CONTROL REGISTER 4
R/W ARINC 429 RX CONTROL REGISTER 5
R/W ARINC 429 RX CONTROL REGISTER 6
R/W ARINC 429 RX CONTROL REGISTER 7
R/W ARINC 429 TX CONTROL REGISTER 0
R/W ARINC 429 TX CONTROL REGISTER 1
R/W ARINC 429 TX CONTROL REGISTER 2
R/W ARINC 429 TX CONTROL REGISTER 3
R/W ARINC 429 TX REPETITION RATE 0
R/W ARINC 429 TX REPETITION RATE 1
R/W ARINC 429 TX REPETITION RATE 2
R/W ARINC 429 TX REPETITION RATE 3
R/W
ARINC 429 Rx INTERRUPT MASK
R/W ARINC 429 Rx FIFO THRESHOLD VALUE
R/W
ARINC 429 LOOPBACK
R ARINC 429 Rx FIFO FULL FLAG
R ARINC 429 Rx FIFO THRESHOLD FLAG
R ARINC 429 Rx FIFO NOT EMPTY FLAG
R ARINC 429 TX SEQUENCE POINTER 0
R ARINC 429 TX SEQUENCE POINTER 1
R ARINC 429 TX SEQUENCE POINTER 2
R ARINC 429 TX SEQUENCE POINTER 3
R/W PENDING INTERRUPT ENABLE REGISTER
R/W
ARINC 429 TX READY INT ENABLE
ARXC0
ARXC1
ARXC2
ARXC3
ARXC4
ARXC5
ARXC6
ARXC7
ATXC0
ATXC1
ATXC2
ATXC3
ATXRR0
ATXRR1
ATXRR2
ATXRR3
AIMR
AFTV
ALOOP
AFFF
AFTF
FFNE
ATXSP0
ATXSP1
ATXSP2
ATXSP3
IMR
ATRIE
Defines channel(s) with pending Interrupt
ARINC 429 Interrupt Vector channel 0
ARINC 429 Interrupt Vector channel 1
ARINC 429 Interrupt Vector channel 2
ARINC 429 Interrupt Vector channel 3
ARINC 429 Interrupt Vector channel 4
ARINC 429 Interrupt Vector channel 5
ARINC 429 Interrupt Vector channel 6
ARINC 429 Interrupt Vector channel 7
Indicates Interrupt type
ARINC 429 Multiplexed FIFO flags
ARINC 429 Transmitter Ready flags
Indicates HI-3200 current status
HI-3200 global configuration
Configures ARINC 429 receive channel 0
Configures ARINC 429 receive channel 1
Configures ARINC 429 receive channel 2
Configures ARINC 429 receive channel 3
Configures ARINC 429 receive channel 4
Configures ARINC 429 receive channel 5
Configures ARINC 429 receive channel 6
Configures ARINC 429 receive channel 7
Configures ARINC 429 transmit channel 0
Configures ARINC 429 transmit channel 1
Configures ARINC 429 transmit channel 2
Configures ARINC 429 transmit channel 3
Sets sequence repeat time for ARINC TX0
Sets sequence repeat time for ARINC TX1
Sets sequence repeat time for ARINC TX2
Sets sequence repeat time for ARINC TX3
Enables Interrupts on AINT pin
Sets flag value for ARINC 429 Receive FIFO
Sets loop-back self-test mode
Indicates which FIFOs are full
Indicates which FIFOs hold > (thresh) messages
Indicates which receive FIFOs hold data
Current address of ARINC transmit sequence 0
Current address of ARINC transmit sequence 1
Current address of ARINC transmit sequence 2
Current address of ARINC transmit sequence 3
Enables Interrupts on INT pin
Enables ARINC 429 TX Ready Interrupts
Fast Access Registers
Memory mapped register access only
* Register is cleared when read (auto clear)
HOLT INTEGRATED CIRCUITS
8







HI-3210 equivalent, schematic
HI-3210
ARINC 429 Received Data FIFO Status Registers
FIFO NOT EMPTY REGISTER
(Address 0x802B)
76543210
MSB
LSB
Bit Name
R/W Default Description
7 AFNE7
R 0 This bit is set to “1” if FIFO #7 contains at least one ARINC 429 message
6 AFNE6
R 0 This bit is set to “1” if FIFO #6 contains at least one ARINC 429 message
5 AFNE5
R 0 This bit is set to “1” if FIFO #5 contains at least one ARINC 429 message
4 AFNE4
R 0 This bit is set to “1” if FIFO #4 contains at least one ARINC 429 message
3 AFNE3
R 0 This bit is set to “1” if FIFO #3 contains at least one ARINC 429 message
2 AFNE2
R 0 This bit is set to “1” if FIFO #2 contains at least one ARINC 429 message
1 AFNE1
R 0 This bit is set to “1” if FIFO #1 contains at least one ARINC 429 message
0 AFNE0
R 0 This bit is set to “1” if FIFO #0 contains at least one ARINC 429 message
FIFO THRESHOLD REGISTER
(Address 0x802A)
76543210
MSB
LSB
Bit Name
R/W Default Description
7 AFTF7
R 0 This bit is set to “1” if FIFO #7 contains > threshold number of ARINC 429 messages
6 AFTF6
R 0 This bit is set to “1” if FIFO #6 contains > threshold number of ARINC 429 messages
5 AFTF5
R 0 This bit is set to “1” if FIFO #5 contains > threshold number of ARINC 429 messages
4 AFTF4
R 0 This bit is set to “1” if FIFO #4 contains > threshold number of ARINC 429 messages
3 AFTF3
R 0 This bit is set to “1” if FIFO #3 contains > threshold number of ARINC 429 messages
2 AFTF2
R 0 This bit is set to “1” if FIFO #2 contains > threshold number of ARINC 429 messages
1 AFTF1
R 0 This bit is set to “1” if FIFO #1 contains > threshold number of ARINC 429 messages
0 AFTF0
R 0 This bit is set to “1” if FIFO #0 contains > threshold number of ARINC 429 messages
FIFO FULL REGISTER
(Address 0x8029)
76543210
MSB
LSB
Bit Name
R/W Default Description
7 AFFF7
R/W 0 This bit is set to “1” if FIFO #7 contains 32 ARINC 429 messages
6 AFFF6
R/W 0 This bit is set to “1” if FIFO #6 contains 32 ARINC 429 messages
5 AFFF5
R/W 0 This bit is set to “1” if FIFO #5 contains 32 ARINC 429 messages
4 AFFF4
R/W 0 This bit is set to “1” if FIFO #4 contains 32 ARINC 429 messages
3 AFFF3
R/W 0 This bit is set to “1” if FIFO #3 contains 32 ARINC 429 messages
2 AFFF2
R/W 0 This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages
1 AFFF1
R/W 0 This bit is set to “1” if FIFO #1 contains 32 ARINC 429 messages
0 AFFF0
R/W 0 This bit is set to “1” if FIFO #0 contains 32 ARINC 429 messages
HOLT INTEGRATED CIRCUITS
16










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