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PDF ( 数据手册 , 数据表 ) 8735-31

零件编号 8735-31
描述 Differential-to-3.3V LVPECL Zero Delay Clock Generator
制造商 IDT
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8735-31 数据手册, 描述, 功能
1:5, Differential-to-3.3V LVPECL Zero
Delay Clock Generator
8735-31
Data Sheet
General Description
The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL
Clock Generator. The 8735-31 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 15.625MHz to 350MHz. The reference
divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
Five differential 3.3V LVPECL output pairs
Selectable differential clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 15.625MHz to 350MHz
Input frequency range: 15.625MHz to 350MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 60ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: 55ps ± 125ps
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PLL_SEL Pullup
CLK0 Pulldown
nCLK0 Pullup
CLK1 Pulldown
nCLK1 Pullup
CLK_SEL Pulldown
FB_IN Pulldown
nFB_IN Pullup
0
1
÷2, ÷4, ÷8, ÷16,
÷32,÷64, ÷128
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
©2016 Integrated Device Technology, Inc
1
Pin Assignment
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
VCCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
8735-31
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
Revision B January 27, 2016







8735-31 pdf, 数据表
Parameter Measurement Information
2V
VCC,
VCCA,
VCCO
SCOPE
Qx
nQx
VEE
1.3V± 0.165V
3.3V Output Load AC Test Circuit
8735-31 Data Sheet
VCC
nCLK0,
nCLK1
CLK0,
CLK1
VEE
V
PP
Cross Points
Differential Input Level
V
CMR
nCLK0,
nCLK1
CLK0,
CLK1
nFB_IN
FB_IN
t (Ø)
Phase Jitter and Static Phase Offset
VOH
VOL
VOH
VOL
nQx
Qx
nQy
Qy
Output Skew
nQ[0:4]
Q[0:4]
tcycle n
tcycle n+1
| |tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
nQ[0:4]
Q[0:4]
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc
8
Revision B January 27, 2016







8735-31 equivalent, schematic
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
8735-31 Data Sheet
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination voltage of
VCCO – 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
• For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
©2016 Integrated Device Technology, Inc
16
Revision B January 27, 2016










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