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PDF ( 数据手册 , 数据表 ) 8732-01

零件编号 8732-01
描述 Low Skew 3.3V LVPECL Clock Generator
制造商 IDT
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8732-01 数据手册, 描述, 功能
Low Voltage, Low Skew
3.3V LVPECL Clock Generator
8732-01
Data Sheet
GENERAL DESCRIPTION
The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock
Generator. The 8732-01 has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential input
levels.The single ended clock input accepts LVCMOS or LVTTL
input levels. The 8732-01 has a fully integrated PLL along with
frequency configurable outputs. An external feedbackinput and
outputs regenerate clocks with “zero delay”.
The 8732-01 has multiple divide select pins for each bank of
outputs along with 3 independent feedback divide select pins
allowing the 8732-01 to function both as a frequency multiplier
and divider. The PLL_SEL input can be usedto bypass the
PLL for test and system debug purposes.In bypass mode,
the input clock is routed around the PLLand into the internal
output dividers.
Features
Ten differential 3.3V LVPECL outputs
Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK1 accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
Output skew: 150ps (maximum)
Static phase offset: -150ps to 150ps
Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCO
QA0
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
VCCO
nQB3
nQA1
VEE
PLL_SEL
VCCO
nQA2
QA3
nQA3
VEE
5 35
6 34
7
ICS8732-01
33
31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
QB2
VEE
MR
VCCO
QB1
nQB0
QB0
VEE
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 22, 2016







8732-01 pdf, 数据表
8732-01 Data Sheet
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin.The ratio
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
©2016 Integrated Device Technology, Inc
8
Revision E January 22, 2016







8732-01 equivalent, schematic
8732-01 Data Sheet
Rev Table
T2
T4A
B
REVISION HISTORY SHEET
Page
1
3
4
5
8
Description of Change
Features Section - changed VCO min. from 200MHz to 250MHz.
Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF.
Qx Output Frequency Table - changed the CLK1 min. column to correlate with
the VCO change.
Absolute Maximum Ratings - changed VO to IO and included Continuous Current
and Surge Current
Added Differential Clock Input Interface in the Application Information section.
Date
5/20/03
C T5A
Power Supply DC Characteristics Table - changed IEE from 240mA max. to
5 165mA max., and ICCA from 14mA max. to 15mA max.
Power Considerations - recalculated Power Dissipation and Junction Tempera-
tures to correspond with Table 5A.
6/23/03
8 Updated LVPECL Output Termination diagrams.
C
10 Added Schematic Layout.
9/24/03
C 1 Block Diagram - changed REF_SEL to CLK_SEL.
3/3/04
C T11
15 Ordering Information Table - corrected Tape & Reel Count to read 500 from 1000. 4/29/04
C T4A
4 Qx Output Frequency Table - changed NOTE 2 from “200MHz” to “175MHz”.
10/19/04
C T11
1 Features Section - added Lead Free bullet.
15 Ordering Information Table - added Lead Free part number and note.
5/23/05
C T5A
5 Power Supply DC Characteristics Table - corrected IEE to read ICC.
5/31/05
T5D
6 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO -
0.9V.
D
11 - 12 Power Considerations - corrected power dissipation to reflect VOH max in Table
4/13/07
5D.
E T11
E T5D
E T11
Updated datasheet’s header/footer with IDT from ICS.
15 Removed ICS prefix from Part/Order Number column.
17 Added Contact Page.
9 VOH Maximum = VCCO - 0.9
Removed ICS in the part number where needed.
15 Ordering Information - removed quantity from tape and reel. Deleted LF note
below the table.
Update header and footer.
7/31/10
5/2/13
1/22/16
©2016 Integrated Device Technology, Inc
16
Revision E January 22, 2016










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