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PDF ( 数据手册 , 数据表 ) 854S006I

零件编号 854S006I
描述 Differential-to-LVDS Fanout Buffer
制造商 IDT
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854S006I 数据手册, 描述, 功能
Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
854S006I
Data Sheet
GENERAL DESCRIPTION
The 854S006I is a low skew, high perfor- mance 1-to-6 Differen-
tial-to-LVDS Fanout Buffer. The CLK, nCLK pair can accept most
standard differential input levels. The 854S006I is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output skew characteristics make the 854S006I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
FEATURES
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
Output skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
BLOCK DIAGRAM
CLK Pullup
nCLK Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
PIN ASSIGNMENT
nCLK
CLK
VDD
VDDO
Q0
nQ0
GND
Q1
nQ1
VDDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 GND
22 VDD
21 VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 Q4
15 VDDO
14 nQ3
13 Q3
854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 19, 2016







854S006I pdf, 数据表
APPLICATION INFORMATION
854S006I Data Sheet
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
DD
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/
DD
R1 = 0.609.
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
©2016 Integrated Device Technology, Inc
8
Revision B January 19, 2016














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