DataSheet8.cn


PDF ( 数据手册 , 数据表 ) 8413S12

零件编号 8413S12
描述 HCSL/ LVCMOS Clock Generator
制造商 IDT
LOGO IDT LOGO 


1 Page

No Preview Available !

8413S12 数据手册, 描述, 功能
HCSL/ LVCMOS Clock Generator
8413S12
DATA SHEET
General Description
Features
The 8413S12 is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12 supports telecommunication,
networking, and storage requirements.
Applications
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Pin Assignment
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
VDDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 ;;;;;;
7
49
48
8 47
9
10
6
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
SLQPP[PP/4)33DFNDJH
REVISION D 1/27/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.







8413S12 pdf, 数据表
8413S12 DATA SHEET
Table 6. Input Frequency Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
FIN
Input
Frequency
CLK, nCLK
XTAL_IN, XTAL_OUT
25
25
Maximum
Units
MHz
MHz
AC Electrical Characteristics
Table 7A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, VDDO_[A:E] = 3.3V ± 5%; and VDD = 3.3V ± 5%, VDDO_G =
VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
PCIe Industry
Minimum Typical Maximum Specification Units
tj
Phase Jitter
Peak-to-Peak;
(PCIe Gen 1) NOTE 1, 4
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
14.27
24.35
86 ps
tREFCLK_HF_R
MS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ= 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.47 3.04
3.10 ps
tREFCLK_LF_R
MS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ= 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.17 0.67
3.0 ps
tREFCLK_RMS Phase Jitter RMS;
(PCIe Gen 3) NOTE 3, 4
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.37 0.79
0.8 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Table 7B. Serial Rapid IO Switch Jitter Specification, VDD = 3.3V ± 5%, VDDO_[A:E] = 3.3V ± 5%; and VDD = 3.3V ± 5%,
VDDO_G = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
IDT sRIO
Minimum Typical Maximum Specification Units
JCLK_REF
Total Phase Jitter, RMS; ƒ= 125MHz, 25MHz Crystal Input,
NOTE 1, 2, 3, 4
HCSL Output Clocks
0.64 1.55
3 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the Serial Rapid IO Application Note section in the datasheet.
NOTE 1: Total phase jitter after applying the evaluation bands to the system transfer function for the IDT sRIO Tsi57x and Tsi620 Product
Families. The transfer function is defined and illustrated in the Serial Rapid IO Application Note section in the datasheet and the IDT hardware
manual of the Tsi57x and Tsi620. Total RMS phase jitter allowed on the reference clock of the Tsi57x and Tsi620 is specified at 3ps (max).
NOTE 2: Evaluation band with sRIO mask applied: 10Hz - 40MHz.
NOTE 3: Total phase jitter includes random and deterministic jitter.
NOTE 4: Jitter data is measured with Agilent E5052A Signal Source Analyzer.
HCSL/ LVCMOS CLOCK GENERATOR
8
REVISION D 1/27/15







8413S12 equivalent, schematic
8413S12 DATA SHEET
Parameter Measurement Information, continued
Differential Measurement Points for Duty Cycle/Period
HCSL/ LVCMOS CLOCK GENERATOR
16
REVISION D 1/27/15










页数 30 页
下载[ 8413S12.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
8413S12HCSL/ LVCMOS Clock GeneratorIDT
IDT
8413S12BHCSL/ LVCMOS Clock GeneratorIDT
IDT
8413S12I-100Clock GeneratorIDT
IDT

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap