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PDF ( 数据手册 , 数据表 ) N84C162

零件编号 N84C162
描述 Supervisory Circuits
制造商 ON Semiconductor
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N84C162 数据手册, 描述, 功能
N84C161, N84C162
Product Preview
Supervisory Circuits with
I2C Serial CMOS EEPROM,
Precision Reset Controller
and Watchdog Timer (16K)
www.onsemi.com
Description
The N84C161/2 is a complete memory and supervisory solution for
microcontroller−based systems. A serial EEPROM memory (16K)
with hardware memory write protection, a system power supervisor
with brown out protection and a watchdog timer are integrated
together in low power CMOS technology. Memory interface is via an
I2C bus.
SOIC−8
CASE 751BD
The 1.6−second watchdog circuit returns a system to a known good
state if a software or hardware glitch halts or “hangs” the system. The
N84C161 watchdog monitors the SDA line, making an additional PC
PIN CONFIGURATION
board trace unnecessary. The lower cost N84C162 does not have a
DC 1
8 VCC
watchdog timer.
The power supply monitor and reset circuit protects memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
RESET
WP
GND
2 N84C161 7
3 N84C162 6
45
RESET
SCL
SDA
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
PIN FUNCTIONS
200 ms after the supply voltage exceeds the reset threshold level. With
Pin Name Function
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, a reset pin can be used as a
debounced input for pushbutton manual reset capability.
The N84C161/2 memory features a 16−byte page. In addition,
DC
RESET
WP
Do Not Connect
Active Low Reset I/O
Write Protect
hardware data protection is provided by a write protect pin WP and by
GND
Ground
a VCC sense circuit that prevents writes to memory whenever VCC falls
below the reset threshold or until VCC reaches the reset threshold
during power up.
These devices are available in a green SOIC−8 package.
Features
SDA
SCL
RESET
VCC
Serial Data/Address
Clock Input
Active High Reset I/O
Power Supply
Watchdog Monitors SDA Signal (N84C161)
400 kHz I2C Bus Compatible
ORDERING INFORMATION
2.7 V to 6 V Operation
For Ordering Information details, see page 11.
Low Power CMOS Technology
16−Byte Page Write Buffer
Built−in Inadvertent Write Protection
VCC Lock Out
Write Protection Pin, WP
1,000,000 Program/Erase Cycles
Manual Reset
100 Year Data Retention
Active High or Low Reset
8−Pin SOIC
Precision Power Supply Voltage Monitor
5 V, 3.3 V and 3 V Systems
Five Threshold Voltage Options
Commercial and Industrial Temperature Ranges
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
September, 2016 − Rev. P0
1
Publication Order Number:
N84C161/D







N84C162 pdf, 数据表
N84C161, N84C162
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the
N84C161/2. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written into
the addressed memory location. The N84C161/2
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
Page Write
The N84C161/2 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted, the
N84C161/2 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
N84C161/2 in a single write cycle.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS
AA
CC
KK
Figure 7. Byte Write Timing
DATA
S
T
O
P
P
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
AAA
CCC
KKK
Figure 8. Page Write Timing
DATA n + 1
A
C
K
S
T
DATA n+15 O
P
P
A
C
K
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
N84C161/2 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the N84C161/2 is still busy with the write
operation, no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can then
proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent memory array programming. If the WP
pin is tied to VCC, the entire memory array is protected and
becomes read only. The N84C161/2 will accept both slave
and byte addresses, but the memory location accessed is
protected from programming by the device’s failure to send
an acknowledge after the first byte of data is received.
www.onsemi.com
8














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