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PDF ( 数据手册 , 数据表 ) N34C04

零件编号 N34C04
描述 4-Kb Serial SPD EEPROM
制造商 ON Semiconductor
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N34C04 数据手册, 描述, 功能
N34C04
4-Kb Serial SPD EEPROM
for DDR4 DIMM
Description
The N34C04 is a 4−Kb serial EEPROM, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
Features
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
Temperature Range: −40°C to +125°C
Supply Range: 1.7 V − 3.6 V
I2C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Low Power CMOS Technology
2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
VCC
SCL
A2, A1, A0
WP
N34C04
SDA
VSS
Figure 1. Functional Symbol
www.onsemi.com
1
UDFN8
MU3 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0 1
A1
(Top View)
A2
VSS
VCC
WP
SCL
SDA
UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
D2U
AZZ
YM
G
UDFN8
D2U
A
ZZ
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
SCL
WP
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
VCC
VSS
DAP
Power Supply
Ground
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
1
Publication Order Number:
N34C04/D







N34C04 pdf, 数据表
N34C04
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
T
A SLAVE
R ADDRESS
T
S
AA
CC
KK
A
C
K
Figure 10. EEPROM Selective Read
DATA n
N
OS
AT
CO
KP
P
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
SDA LINE
SLAVE
A
C
K
AAA
CCC
KKK
DATA n
DATA n+1
DATA n+2
Figure 11. EEPROM Sequential Read
N
OS
AT
CO
KP
P
DATA n+x
Software Write Protection
Each 1−Kb memory block can be individually protected
against Write requests. Block identities are:
Block 0: byte address 0x00...0x7F (SPD page address = 0)
Block 1: byte address 0x80...0xFF (SPD page address = 0)
Block 2: byte address 0x00...0x7F (SPD page address = 1)
Block 3: byte address 0x80...0xFF (SPD page address = 1)
Block Software Write Protection (SWP) flags can be set
or cleared in the presence of a very high voltage VHV on
address pin A0. The VHV condition must be established on
pin A0 before the START and maintained just beyond the
STOP. The D.C. OPERATING CONDITIONS for SWP
operations are shown in Table 10.
SWP command details are listed in Tables 11a and 11b.
SWP Slave addresses follow the standard I2C convention,
i.e. to read the state of a SWP flag, the LSB of the Slave
address must be ‘1’, and to set or clear a flag, it must be ‘0’.
For Set/Clear commands a dummy byte address and dummy
data byte must be provided (Figure 12). In contrast to a
regular memory Read, a SWP Read does not return data.
Instead the N34C04 will respond with NoACK if the flag is
set and with ACK if the flag is not set (Figure 13).
Table 10. SWPn AND CWP D.C. OPERATION CONDITION
Symbol
Parameter
Test Conditions
DVHV
IHVD
VHV
A0 Overdrive (VHV − VCC)
A0 High Voltage Detector Current
A0 Very High Voltage
1.7 V < VCC < 3.6 V
Min Max Units
4.8 V
0.1 mA
7 10 V
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