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PDF ( 数据手册 , 数据表 ) N24C08

零件编号 N24C08
描述 I2C CMOS Serial EEPROM
制造商 ON Semiconductor
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N24C08 数据手册, 描述, 功能
N24C02, N24C04, N24C08,
N24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I2C CMOS Serial EEPROM
Description
The N24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support the Standard (100 kHz), Fast (400 kHz) and Fast−Plus
(1 MHz) I2C protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
N24C02, four N24C04, two N24C08 and one N24C16 device on the
same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V / 1.6 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Fast Write Time (4 ms max)
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
More than 1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Automotive Grade 1 Temperature Range
US 8−Lead Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATION
N24C__
16 / 08 / 04 / 02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
US8 (U) (Top View)
www.onsemi.com
US8
U SUFFIX
CASE 493
MARKING DIAGRAM
8
XX MG
G
1
XX = Specific Device Code*
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
* See Ordering Information section for the
Specific Device Marking Code
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 1
1
Publication Order Number:
N24C02/D







N24C08 pdf, 数据表
N24C02, N24C04, N24C08, N24C16
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the N24Cxx will interpret this as a request for data residing
at the current byte address in memory. The N24Cxx will
acknowledge the Slave address, will immediately shift out
the data residing at the current address, and will then wait for
the Master to respond. If the Master does not acknowledge
the data (NoACK) and then follows up with a STOP
condition (Figure 10), the N24Cxx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the N24Cxx
acknowledges the byte address, the Master device resends
the START condition and the slave address, this time with
the R/W bit set to one. The N24Cxx then responds with its
acknowledge and sends the requested data byte. The Master
device does not acknowledge the data (NoACK) but will
generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1st
data byte, then the N24Cxx will continue transmitting data
residing at subsequent locations until the Master responds
with a NoACK, followed by a STOP (Figure 12). In contrast
to Page Write, during Sequential Read the address count will
automatically increment to and then wrap−around at end of
memory (rather than end of page).
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
N
O
S
AT
CO
KP
SP
SLAVE
A
C D ATA
K BYTE
SCL 8 9
SDA
8th Bit
DATA OUT
NO ACK
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
SLAVE
SLAVE
ADDRESS
ADDRESS
BYTE
S
T
A SLAVE
R ADDRESS
T
S
AA
CC
KK
Figure 11. Selective Read Sequence
A
C
K
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
A AA
C CC
K KK
SLAVE
A
C D ATA
K BYTE
n
D ATA
BYTE
n+1
D ATA
BYTE
n+2
Figure 12. Sequential Read Sequence
STOP
D ATA
BYTE
N
O
S
AT
CO
KP
P
D ATA
BYTE
n+x
N
O
S
AT
CO
KP
P
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