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PDF ( 数据手册 , 数据表 ) N24C32

零件编号 N24C32
描述 32 Kb I2C CMOS Serial EEPROM
制造商 ON Semiconductor
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N24C32 数据手册, 描述, 功能
N24C32
32 Kb I2C CMOS Serial
EEPROM
Description
The N24C32 is a 32 Kb CMOS Serial EEPROM device, organized
internally as 128 pages of 32 bytes each. This device supports the
Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C
protocol.
Data is written by providing a starting address, then loading 1 to 32
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
N24C32 devices on the same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V / 1.6 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Fast Write Time (4 ms max)
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Automotive Grade 1 Temperature Range
US 8−lead Package
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
www.onsemi.com
US8
U SUFFIX
CASE 493
PIN CONFIGURATIONS
A0
A1
A2
VSS
1
VCC
WP
SCL
SDA
US8 (U)
(Top View)
MARKING DIAGRAM
8
XX MG
G
1
XX = Specific Device Code*
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
* See Ordering Information section for the
Specific Device Marking Code
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 1
1
Publication Order Number:
N24C32/D







N24C32 pdf, 数据表
N24C32
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
BUS ACTIVITY: S
T
A
MASTER R
T
S
SLAVE
SLAVE
ADDRESS
A
C
K
DATA
BYTE
N
O
S
AT
CO
KP
P
SCL 8 9
SDA
8th Bit
DATA OUT
NO ACK
Figure 10. Immediate Read Sequence and Timing
STOP
BUS ACTIVITY: S
T
A
MASTER R
T
S
SLAVE
SLAVE
ADDRESS
ADDRESS
BYTE
ADDRESS
BYTE
S
T
A SLAVE
R ADDRESS
T
S
AAA
CCC
KKK
Figure 11. Selective Read Sequence
A
C
K
DATA
BYTE
N
OS
AT
CO
KP
P
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
AA A
CC C
KK K
SLAVE
A
C DATA
K BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
Figure 12. Sequential Read Sequence
DATA
BYTE
n+x
N
OS
AT
CO
KP
P
www.onsemi.com
8














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