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PDF ( 数据手册 , 数据表 ) N01S830BA

零件编号 N01S830BA
描述 1 Mb Ultra-Low Power Serial SRAM
制造商 ON Semiconductor
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N01S830BA 数据手册, 描述, 功能
N01S830HA, N01S830BA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory. The devices can operate over a wide temperature range of
−40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead
TSSOP package. The N01S830xA device has two different variations,
a HOLD version that allows communication to the device to be paused
and a battery back-up (BBU) version to be used with a battery to retain
data when power is lost.
Features
Power Supply Range: 2.5 to 5.5 V
Very Low Typical Standby Current < 4 mA at +85°C
Very Low Operating Current < 10 mA
Simple Serial Interface
Single-bit SPI Access
DUAL-bit and QUAD-bit SPI-like Access
Flexible Operating Modes
Word Mode
Page Mode
Burst Mode (Full Array)
High Frequency Read and Write Operation
Clock Frequency up to 20 MHz
Functional Options
HOLD Pin for Pausing Operation
VBAT Pin for Battery−Back up
Built-in Write Protection (CS High)
High Reliability
Unlimited Write Cycles
Temperature Ranges Supported
Industrial (I): TA = −40°C to +85°C
Automotive (E): TA = −40°C to +125°C
These Devices are Pb−Free and are RoHS Compliant
Green TSSOP
www.onsemi.com
TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
CS
SO / SIO1
NC / SIO2
VSS
18
27
36
45
HOLD Version
VCC
HOLD / SIO3
SCK
SI / SIO0
CS
SO / SIO1
NC
VSS
18
27
36
45
BBU Version
VCC
VBAT
SCK
SI / SIO0
ORDERING INFORMATION
Device
Package
Shipping
N01S830HAT22I
N01S830BAT22I
N01S830HAT22IT
N01S830BAT22IT
TSSOP−8
(Pb−Free)
100 Units / Tube
TSSOP−8
(Pb−Free)
3000 / Tape
& Reel
N01S830HAT22E
N01S830BAT22E
TSSOP−8
(Pb−Free)
100 Units / Tube
N01S830HAT22ET TSSOP−8
N01S830BAT22ET (Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
Publication Order Number:
N01S830HA/D







N01S830BA pdf, 数据表
N01S830HA, N01S830BA
CS
SCK
0123
SIO[3:0]
Instruction Mode Bits
C1 C0 H L
Notes: C[1:0] = 05h
MSB
Figure 11. QUAD Read Mode Register Sequence (RDMR)
Write Mode Register (WRMR)
This instruction provides the ability to write the mode
register. The Write Mode Register operation is executed by
driving CS low, then sending the WRMR instruction to the
CS
device. Immediately after the instruction, the data is driven
to the device on the SO (SIO0-3) pin(s). To complete the
operation, drive CS high to terminate the register write.
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Mode Register Data In
0000000176543210
SO High−Z
Figure 12. SPI Write Mode Register Sequence
CS
SCK
SIO[1:0]
01234567
Instruction
Mode Bits
C3 C2 C1 C0 H H L
L
Notes: C[3:0] = 01h
MSB
Figure 13. DUAL Write Mode Register Sequence
CS
SCK
0123
SIO[3:0]
Instruction Mode Bits
C1 C0 H L
MSB
Notes: C[1:0] = 01h
Figure 14. QUAD Write Mode Register Sequence
www.onsemi.com
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