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PDF ( 数据手册 , 数据表 ) 49LF004B

零件编号 49LF004B
描述 SST49LF004B
制造商 Silicon Storage Technology
LOGO Silicon Storage Technology LOGO 


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49LF004B 数据手册, 描述, 功能
4 Mbit LPC Firmware Flash
SST49LF004B
FEATURES:
SST49LF004B4Mb LPC Firmware memory
Data Sheet
• SST49LF004B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.1
– Supports Single-Byte LPC Memory and
Firmware Memory Cycle Types
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
• LPC Interface Mode
– 5-signal LPC bus interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block
write-lock and lock-down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming in-system on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 40-lead TSOP (10mm x 20mm)
PRODUCT DESCRIPTION
The SST49LF004B flash memory device is designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS applications. The
SST49LF004B device complies with Intel’s LPC Interface
Specification 1.1, supporting single-byte Firmware Memory
and LPC Memory cycle types.
The SST49LF004B is backward compatible to the
SST49LF00xA Firmware Hub and the SST49LF0x0A LPC
Flash. In this document, FWH mode in the SST49LF00xA
specification is referenced as the Firmware Memory Read/
Write cycle and LPC mode in the SST49LF0x0A specifica-
tion is referenced as the LPC Memory Read/Write cycle.
Two interface modes are supported by the SST49LF004B:
LPC mode (Firmware Memory and LPC Memory cycle
types) for in-system operations and Parallel Programming
(PP) mode to interface with programming equipment.
The SST49LF004B flash memory device is manufactured
with SST’s proprietary, high-performance SuperFlash tech-
nology. The split-gate cell design and thick-oxide tunneling
injector attain greater reliability and manufacturability com-
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
1
pared with alternative approaches. The SST49LF004B
device significantly improves performance and reliability,
while lowering power consumption. The SST49LF004B
device writes (Program or Erase) with a single 3.0-3.6V
power supply.
The SST49LF004B provides a maximum Byte-Program
time of 20 µsec. The entire memory can be erased and
programmed byte-by-byte in 8 seconds when using status
detection features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent writes, the SST49LF004B device has
on-chip hardware and software write protection schemes. It
is offered with a typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST49LF004B uses less energy during Erase and
Program than alternative flash memory technologies. The
total energy consumed is a function of the applied voltage,
current and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.







49LF004B pdf, 数据表
Data Sheet
PIN DESCRIPTIONS
4 Mbit LPC Firmware Flash
SST49LF004B
TABLE 1: PIN DESCRIPTION
Symbol
LCLK
LAD[3:0]
LFRAME#
Pin Name
Clock
Address and
Data
Frame
MODE
Interface
Mode Select
RST#
INIT#
ID[3:0]
Reset
Initialize
Identification
Inputs
GPI[4:0] General
Purpose Inputs
TBL#
Top Block Lock
WP#
Write Protect
R/C#
A10-A0
Row/Column
Select
Address
DQ7-DQ0 Data
OE#
WE#
RES
VDD
VSS
NC
Output Enable
Write Enable
Reserved
Power Supply
Ground
No Connection
1. I = Input, O = Output
Type1
I
I/O
I
I
I
I
I
I
I
I
I
I
I/O
I
I
PWR
PWR
Interface
PP LPC Functions
X To provide a clock input to the control unit
X To provide LPC bus information such as addresses and command
inputs/outputs data.
X To indicate start of a data transfer operation; also used to abort an LPC
cycle in progress.
X X This pin determines which interface is operational. When held high, program-
mer mode is enabled and when held low, LPC mode is enabled. This pin must
be set at power-up or before returning from reset and must not change during
device operation. This pin must be held high (VIH) for PP mode and low (VIL)
for LPC mode. This pin is internally pulled-down with a resistor between 20-
100 KΩ.
X X To reset the operation of the device
X This is the second reset pin for in-system use.
This pin functions identically to RST#.
X These four pins are part of the mechanism that allows multiple parts to be
attached to the same bus. The strapping of these pins is used to identify the
component. The boot device must have ID[3:0]=0000, all subsequent devices
should use sequential count-up strapping. These pins are internally pulled-down
with a resistor between 20-100 KΩ.
X These individual inputs can be used for additional board flexibility. The state of
these pins can be read through LPC registers. These inputs should be at their
desired state before the start of the LPC clock cycle during which the read is
attempted, and should remain in place until the end of the Read cycle.
Unused GPI pins must not be floated.
X When low, prevents programming to the boot block sectors at the top of the
device memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
X When low, prevents programming to all but the highest addressable blocks.
When WP# is high it disables hardware write protection for these blocks. This
pin cannot be left unconnected.
X Select for the Programming interface, this pin determines whether the
address pins are pointing to the row addresses, or to the column addresses.
X Inputs for low-order addresses during Read and Write operations. Addresses
are internally latched during a Write cycle. For the programming interface,
these addresses are latched by R/C# and share the same pins as the high-
order address inputs.
X To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# is high.
X To gate the data output buffers.
X To control the Write operations.
X These pins must be left unconnected.
X X To provide power supply (3.0-3.6V)
X X Circuit ground (0V reference)
N/A N/A Unconnected pins.
T1.0 1232
©2003 Silicon Storage Technology, Inc.
8
S71232-02-000
12/03







49LF004B equivalent, schematic
Data Sheet
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles after
the start of a bus cycle, the cycle will be terminated. The
host may drive LAD[3:0] with '1111b' (ABORT nibble) to
return the interface to ready mode. The ABORT only
affects the current bus cycle. For a multi-cycle command
sequence, such as the Erase or Program SDP commands,
ABORT doesn't interrupt the entire command sequence,
only the current bus cycle of the command sequence. The
host can re-send the bus cycle for the aborted command
and continue the SDP command sequence after the device
is ready again.
Response to Invalid Fields for Firmware
Memory Cycle
The SST49LF004B will not explicitly indicate that it has
received invalid field sequences. The response to specific
invalid fields or sequences is as follows:
ID mismatch: If the IDSEL field does not match ID[3:0],
the device will ignore the cycle. See Multiple Device Selec-
tion section for details.
Address out of range: The address sequence is 7
fields long (28 bits) for Firmware Memory bus cycles, but
only A22 and A18:A0 will be decoded by SST49LF004B.
Address A22 has the special function of directing reads and
writes to the flash core (A22=1) or to the register space
(A22=0).
Invalid MSIZE field: If the device receives an invalid
MSIZE field during a Firmware Memory Read or Write
cycle, the device will reset and no operation will be
attempted. The SST49LF004B will not generate any kind
of response in this situation. Invalid size fields for a Firm-
ware Memory cycle are any data other than 0000b.
Once valid START, IDSEL, and MSIZE fields are received,
the SST49LF004B will always complete the bus cycle.
However, if the device is busy performing a flash Erase or
Program operation, no new Write command (memory write
or register write) will be executed.
4 Mbit LPC Firmware Flash
SST49LF004B
Response to Invalid Fields for LPC
Memory Cycle
ID mismatch: ID information is included in the address bits
of every LPC Memory cycle. Address bits A23, A21:A19 are
used to select the device with proper IDs. The
SST49LF004B will compare the ID bits in the address field
with ID[3:0]. If the ID bits in the address do not correspond
to the hardware ID pins the device will ignore the cycle. See
Multiple Device Selection section for details.
Address out of range: The address sequence is 8 fields
long (32 bits). Address bits A23, A21:A19 are used to select
the device with proper IDs. The SST49LF004B responds to
address range FFFF FFFFH to FF80 0000H and
000F FFFFH to 000E 0000H during LPC memory cycle
transfers. Address A22 has the special function of directing
reads and writes to the flash core (A22=1) or to the register
space (A22=0).
Once valid START, CYCTYPE + DIR, and address range
(including ID bits) are received, the SST49LF004B will
always complete the bus cycle. However, if the device is
busy performing a flash Erase or Program operation, no
new internal Write command (memory Write or register
Write) will be executed. As long as the states of LAD[3:0]
and LFRAME# are known, the response of the
SST49LF004B to signals received during the LPC cycle
should be predictable.
©2003 Silicon Storage Technology, Inc.
16
S71232-02-000
12/03










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